Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
    reg [2:0] cnt;
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            cnt<=0;
        else
            cnt<=(cnt==5)? 0:cnt+1;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            data<=0;
        else
            data<=~(cnt==0|cnt==1|cnt==3);
    end
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
    reg [2:0] cnt6;
    
    always @(posedge clk or negedge rst_n) 
        if (!rst_n)
            cnt6 <= 0;
        else if (cnt6 == 3'd5)
            cnt6 <= 0;
        else
            cnt6 <= cnt6 + 1'b1;   
    
    always @(posedge clk or negedge rst_n) 
        if (!rst_n)
            data <= 1'b0;
        else 
//             case(cnt6)
//                 0 : data <= 1'b0;
//                 1 : data <= 1'b0;
//                 3 : data <= 1'b0;
//                 default : data <= 1'b1;
//             endcase
                
            if (cnt6 == 3'd0 || cnt6 == 3'd1 || cnt6 == 3'd3)
            data <= 1'b0;
        else if (cnt6 == 3'd2 || cnt6 == 3'd4 || cnt6 == 3'd5)
            data <= 1'b1;
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
    
    wire [5:0] seq;
    reg [2:0] cnt;
    
    assign seq = {1'b1,1'b1,1'b0,1'b1,1'b0,1'b0};
    
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            cnt <= 0;
    else if(cnt == 3'd5)
        cnt <= 0;
    else
        cnt <= cnt + 1'b1;
    
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            data <= 0;
        else
            data <= seq[cnt];
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
    reg [5:0]tem = 6'b110100;
    integer i = 0;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin i<=0;data<=0;end
        else begin
            if(i == 6)i=0;
            data <= tem[i];
            i = i + 1;      
        end
    end
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
	reg [3:0] cnt;

	always @ (posedge clk or negedge rst_n) begin
		if (!rst_n)
			cnt <= 0;
		else if (cnt == 4'd5)
			cnt <= 0;
		else
			cnt <= cnt + 1'b1;	
	end

	always @ (posedge clk or negedge rst_n) begin
		if (!rst_n)
			data <= 0;
		else
			data = (cnt == 4'd2 || cnt == 4'd4 || cnt == 4'd5)? 1 : 0;
	end
	
endmodule