Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);
    reg [1:0] cnt;
    reg [3:0] d_reg;
    reg valid_in_reg;
    
    always @(posedge clk or negedge rst) begin
        if(!rst)
            valid_in_reg<=0;
        else 
            valid_in_reg<=(cnt==3);
    end
    
    always @(posedge clk or negedge rst) begin
        if(!rst)
            cnt<=0;
        else 
            cnt<=(cnt==3)? 0:cnt+1;
    end
    
    always @(posedge clk or negedge rst) begin
        if(!rst)
            d_reg<=0;
        else
            d_reg<=(cnt==3)? d:d_reg<<1;
    end
    
    assign valid_in=valid_in_reg;
    assign dout=d_reg[3];
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
    reg       valid;
    reg [3:0] data_reg;
    reg [1:0] cnt;
    always@(posedge clk or negedge rst) begin
        if(!rst)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end
    always@(posedge clk or negedge rst) begin
        if(!rst)
            valid <= 0;
        else
            valid <= (cnt==3)? 1 : 0;
    end
    always@(posedge clk or negedge rst) begin
        if(!rst)
            data_reg <= 0;
        else
            data_reg <= (cnt==3)? d : (data_reg<<1);
    end
    assign   valid_in = valid;
    assign   dout     = data_reg[3];

//*************code***********//

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output reg dout
	);

//*************code***********//
    reg [3:0]dout_re;
    reg [1:0] cnt = 0;
    reg valid_in_re;
    always@(posedge clk or negedge rst)begin
        if(rst == 0)begin
           
            valid_in_re <= 0;
            cnt <= 0;
            dout_re<= 0;
        end
        else begin
            if(cnt == 3)begin
                valid_in_re <= 1;
                dout_re <= d;
                cnt <= 0;
            end
            else begin
                valid_in_re <= 0;
                dout_re <= d;
                cnt <= cnt + 1;
            end
        end
    end

    always@(posedge clk or negedge rst)begin
        if(rst == 0)begin
            dout <= 0;
        end
        else if( cnt == 0)begin
            dout <= dout_re[2];
        end
        else if(cnt == 1)begin
            dout <= dout_re[1];
        end
        else if(cnt == 2)begin
            dout <= dout_re[0];
        end
        else if(cnt == 3)begin
            dout <= d[3];
        end
    end
 //   assign dout = dout_re[cnt];
    assign valid_in = valid_in_re;
//*************code***********//

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
    reg [1:0] cnt;
    reg [3:0] data;
    reg valid_in_r;
    always @(posedge clk or negedge rst)begin
        if(!rst)begin
            cnt <= 2'b0; 
        end
        else begin
            cnt <=  cnt + 1; 
        end
    end
    
    always @(posedge clk or negedge rst)begin
        if(!rst)begin
            data <= 3'b0; 
            valid_in_r <= 1'b0;
        end
        else if(cnt == 2'b11)begin
            data <= d;
            valid_in_r <= 1'b1;
        end
        else begin
            data <= data <<1;
            valid_in_r <=1'b0;
        end
    end
    assign dout = data[3];
    assign valid_in = valid_in_r;

//*************code***********//

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);
    reg[2:0] cnt;
    reg[3:0] d_reg;
//*************code***********//
    always@(posedge clk or negedge rst) begin
        if(!rst)
            cnt <= 'd0;
        else
            cnt <= (cnt=='d3)?'d0:cnt+1'b1;
    end
    always@(posedge clk or negedge rst) begin
        if(!rst)
            d_reg <= 'd0;
        else
            d_reg <= (cnt=='d3)?d:d_reg<<1;
    end
    reg vald_in;
    always@(posedge clk or negedge rst) begin
        if(!rst)begin
            vald_in<=1'b0;end
        else begin
            vald_in <= (cnt=='d3)?1'b1:1'b0;
        end
    end
    assign valid_in = vald_in;
    assign dout = d_reg[3];
//*************code***********//

endmodule