VL73. 串行进位加法器
描述
module add_half( input A , input B , output wire S , output wire C ); assign S = A ^ B; assign C = A & B; endmodule /***************************************************************/ module add_full( input A , input B , input Ci , output wire S , output wire Co ); wire c_1; wire c_2; wire sum_1; add_half add_half_1( .A (A), .B (B), .S (sum_1), .C (c_1) ); add_half add_half_2( .A (sum_1), .B (Ci), .S (S), .C (c_2) ); assign Co = c_1 | c_2; endmodule
输入描述
input [3:0] A ,输出描述
output wire [3:0] S ,Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module add_4(
input [3:0] A ,
input [3:0] B ,
input Ci ,
output wire [3:0] S ,
output wire Co
);
wire [3:0] c;
assign Co = c[3];
generate
genvar i;
for(i=0;i<4;i=i+1)begin:add_full
add_full add(.A(A[i]),.B(B[i]),.Ci(i==0 ? Ci : c[i-1]),.S(S[i]),.Co(c[i]));
end
endgenerate
endmodule
module add_full(
input A ,
input B ,
input Ci ,
output wire S ,
output wire Co
);
wire c_1;
wire c_2;
wire sum_1;
add_half add_half_1(
.A (A),
.B (B),
.S (sum_1),
.C (c_1)
);
add_half add_half_2(
.A (sum_1),
.B (Ci),
.S (S),
.C (c_2)
);
assign Co = c_1 | c_2;
endmodule
module add_half(
input A ,
input B ,
output wire S ,
output wire C
);
assign S = A ^ B;
assign C = A & B;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
`timescale 1ns/1ns
module add_half(
input A ,
input B ,
output wire S ,
output wire C
);
assign S = A ^ B;
assign C = A & B;
endmodule
/***************************************************************/
module add_full(
input A ,
input B ,
input Ci ,
output wire S ,
output wire Co
);
wire S_tmp, C_tmp1,C_tmp2;
add_half u_add_half1(
.A(A) ,
.B(B) ,
.S(S_tmp) ,
.C(C_tmp1)
);
add_half u_add_half2(
.A(S_tmp) ,
.B(Ci) ,
.S(S) ,
.C(C_tmp2)
);
assign Co = C_tmp1 | C_tmp2;
endmodule
module add_4(
input [3:0] A ,
input [3:0] B ,
input Ci ,
output wire [3:0] S ,
output wire Co
);
wire [4:0] C_tmp;
assign C_tmp[0] = Ci;
genvar i;
generate
for(i=0;i<=3;i=i+1) begin: add_serial
add_full u_add_full(.A(A[i]), .B(B[i]), .Ci(C_tmp[i]), .S(S[i]), .Co(C_tmp[i+1]));
end
endgenerate
assign Co = C_tmp[4];
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05
`timescale 1ns/1ns
module add_half(
input A ,
input B ,
output wire S ,
output wire C
);
assign S = A ^ B;
assign C = A & B;
endmodule
module add_full(
input A ,
input B ,
input Ci ,
output wire S ,
output wire Co
);
wire c_1;
wire c_2;
wire sum_1;
add_half add_half_1(
.A (A),
.B (B),
.S (sum_1),
.C (c_1)
);
add_half add_half_2(
.A (sum_1),
.B (Ci),
.S (S),
.C (c_2)
);
assign Co = c_1 | c_2;
endmodule
module add_4(
input [3:0] A ,
input [3:0] B ,
input Ci ,
output wire [3:0] S ,
output wire Co
);
wire tem,tem1,tem2;
add_full aaa(A[0],B[0],Ci,S[0],tem);
add_full bbb(A[1],B[1],tem,S[1],tem1);
add_full ccc(A[2],B[2],tem1,S[2],tem2);
add_full ddd(A[3],B[3],tem2,S[3],Co);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05
`timescale 1ns/1ns
module add_4(
input [3:0] A ,
input [3:0] B ,
input Ci ,
output wire [3:0] S ,
output wire Co
);
wire mid_2,mid_3,mid_4;
add_full add_full_1(
.A(A[0]),
.B(B[0]),
.Ci(Ci),
.S(S[0]),
.Co(mid_2));
add_full add_full_2(
.A(A[1]),
.B(B[1]),
.Ci(mid_2),
.S(S[1]),
.Co(mid_3));
add_full add_full_3(
.A(A[2]),
.B(B[2]),
.Ci(mid_3),
.S(S[2]),
.Co(mid_4));
add_full add_full_4(
.A(A[3]),
.B(B[3]),
.Ci(mid_4),
.S(S[3]),
.Co(Co));
endmodule
/***************************************************************/
module add_full(
input A ,
input B ,
input Ci ,
output wire S ,
output wire Co
);
wire c_1;
wire c_2;
wire sum_1;
add_half add_half_1(
.A (A),
.B (B),
.S (sum_1),
.C (c_1)
);
add_half add_half_2(
.A (sum_1),
.B (Ci),
.S (S),
.C (c_2)
);
assign Co = c_1 | c_2;
endmodule
module add_half(
input A ,
input B ,
output wire S ,
output wire C
);
assign S = A ^ B;
assign C = A & B;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05
`timescale 1ns/1ns
module add_4(
input [3:0] A ,
input [3:0] B ,
input Ci ,
output wire [3:0] S ,
output wire Co
);
wire [3:0] C;
add_full u0_add_full(
.A(A[0]),
.B(B[0]),
.Ci(Ci),
.S(S[0]),
.Co(C[0])
);
add_full u1_add_full(
.A(A[1]),
.B(B[1]),
.Ci(C[0]),
.S(S[1]),
.Co(C[1])
);
add_full u2_add_full(
.A(A[2]),
.B(B[2]),
.Ci(C[1]),
.S(S[2]),
.Co(C[2])
);
add_full u3_add_full(
.A(A[3]),
.B(B[3]),
.Ci(C[2]),
.S(S[3]),
.Co(C[3])
);
assign Co = C[3];
endmodule
module add_half(
input A ,
input B ,
output wire S ,
output wire C
);
assign S = A ^ B;
assign C = A & B;
endmodule
/***************************************************************/
module add_full(
input A ,
input B ,
input Ci ,
output wire S ,
output wire Co
);
wire c_1;
wire c_2;
wire sum_1;
add_half add_half_1(
.A (A),
.B (B),
.S (sum_1),
.C (c_1)
);
add_half add_half_2(
.A (sum_1),
.B (Ci),
.S (S),
.C (c_2)
);
assign Co = c_1 | c_2;
endmodule