Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
    reg rst_n_sync_r1,rst_n_sync_r2;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            {rst_n_sync_r1,rst_n_sync_r2} <= 'd0;
        end
        else begin
            {rst_n_sync_r1,rst_n_sync_r2} <= {1'b1,rst_n_sync_r1};
        end
    end
    
    always@(posedge clk or negedge rst_n_sync_r2) begin
        if(!rst_n_sync_r2) begin
            dout <= 1'b0;
        end
        else begin
            dout <= d;
        end
    end

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
    reg rst_1;
    reg rst_2;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            rst_1<=0;
            rst_2<=0;
        end
        else begin
            rst_1<=1'b1;
            rst_2<=rst_1;
        end
    end
    
    always @(posedge clk or negedge rst_2) begin
        if(!rst_2) begin
            dout<=0;
        end
        else begin
            dout<=d;
        end
    end 
    

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );
    reg rstn_reg, rstn_reg_1;
    
    //异步复位,同步释放
    always @(posedge clk, negedge rst_n) begin
        if(!rst_n) begin
            rstn_reg <= 1'b0;
            rstn_reg_1 <= 1'b0;   
        end
        else begin
            rstn_reg <= rst_n;
            rstn_reg_1 <= rstn_reg;  
        end
        
    end
    
    //赋值
    always @(posedge clk, negedge rstn_reg_1) begin
        if(!rstn_reg_1) begin
            dout <= 1'b0;
        end
        else
            dout <= d;
        
    end    

//*************code***********//


//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
reg rst_n_r;
reg rst_n_rr;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            rst_n_r <= 1'b0;
            rst_n_rr<= 1'b0;
        end
        else begin
            rst_n_r <= 1'b1;
            rst_n_rr<= rst_n_r;
        end
    end
    
    always @(posedge clk or negedge rst_n_rr) begin
        if(!rst_n_rr) begin
            dout <= 1'b0;
        end
        else begin
            dout <= d;
        end
    end
    

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
reg rs1,rs2;
    always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
                begin
                    rs1<=0;
                    rs2<=0;
                end
            else
                begin
                    rs1<=1;
                    rs2<=rs1;
                end
        end
    always@(posedge clk or negedge rs2)
        begin
            if(!rs2)
                dout<=0;
            else
                dout<=d;
        end
                          
        

//*************code***********//
endmodule