Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
    assign {Co,S} = A + B + Ci;
    
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
    wire S_tmp, C_tmp1,C_tmp2;
    add_half u_add_half1(
        .A(A)   ,
        .B(B)   ,
 
        .S(S_tmp)   ,
        .C(C_tmp1)   
);
    add_half u_add_half2(
        .A(S_tmp)   ,
        .B(Ci)   ,
 
        .S(S)   ,
        .C(C_tmp2)   
);
    assign Co = C_tmp1 | C_tmp2;
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
    wire hS, hC1, hC2;
    add_half add_h1 (
        A,
        B,
        hS,
        hC1
    );
    
    add_half add_h2 (
        hS,
        Ci,
        S,
        hC2
    );
    assign Co = hC1 | hC2;
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
wire c_1;
wire c_2;
wire sum_1;
 
add_half add_half_1(
   .A   (A),
   .B   (B),
          
   .S   (sum_1),
   .C   (c_1)  
);
add_half add_half_2(
   .A   (sum_1),
   .B   (Ci),
          
   .S   (S),
   .C   (c_2)  
);
 
assign Co = c_1 | c_2;
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
    
    wire AaddB;
    wire Co1;
    
    add_half mod_add_half1(
        .A(A),
        .B(B),
        .S(AaddB),
        .C(Co1)
    );
    
    add_half mod_add_half2(
        .A(AaddB),
        .B(Ci),
        .S(S),
        .C(Co2)
    );
    
    assign Co = Co1 | Co2;
    
endmodule