VL69. 脉冲同步器（快到慢）
描述
sig_a 是 clka（300M）时钟域的一个单时钟脉冲信号（高电平持续一个时钟clka周期），请设计脉冲同步电路，将sig_a信号同步到时钟域 clkb（100M）中，产生sig_b单时钟脉冲信号（高电平持续一个时钟clkb周期）输出。请用 Verilog 代码描述。
输入描述
input clka ,输出描述
output sig_bVerilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 100ps/100ps
module pulse_detect(
input clka ,
input clkb ,
input rst_n ,
input sig_a ,
output sig_b
);
reg sig_a1;
reg sig_b1,sig_b2,sig_b3;
always@(posedge clka or negedge rst_n) begin
if(!rst_n) begin
sig_a1<=0;
end
else begin
if(sig_a) begin
sig_a1<=1;
end
else if(sig_b2) begin
sig_a1<=0;
end
else begin
sig_a1<=sig_a1;
end
end
end
always@(posedge clkb or negedge rst_n) begin
if(!rst_n) begin
{sig_b3,sig_b2,sig_b1}<=3'd0;
end
else begin
{sig_b3,sig_b2,sig_b1}<={sig_b2,sig_b1,sig_a1};
end
end
assign sig_b=sig_b2&(~sig_b3);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 100ps/100ps
module pulse_detect(
input clka ,
input clkb ,
input rst_n ,
input sig_a ,
output sig_b
);
reg sig_a_rev;
reg sig_b_rev,sig_b_rev_1,sig_b_rev_2;
always @(posedge clka or negedge rst_n)begin
if(!rst_n) sig_a_rev<='b0;
else if(sig_a) sig_a_rev<=~sig_a_rev;
else sig_a_rev<=sig_a_rev;
end
always @(posedge clkb or negedge rst_n)begin
if(!rst_n)begin
sig_b_rev<='b0;
sig_b_rev_1<='b0;
sig_b_rev_2<='b0;
end
else begin
sig_b_rev<=sig_a_rev;
sig_b_rev_1<=sig_b_rev;
sig_b_rev_2<=sig_b_rev_1;
end
end
assign sig_b=sig_b_rev_1^sig_b_rev_2;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 100ps/100ps
module pulse_detect(
input clka ,
input clkb ,
input rst_n ,
input sig_a ,
output sig_b
);
reg data;
reg buffer1, buffer2;
always@(posedge clka or negedge rst_n) begin
if(!rst_n)
data <= 0;
else if(sig_a)
data <= ~data;
else if(!sig_a)
data <= data;
end
always@(posedge clkb or negedge rst_n) begin
if(!rst_n)begin
buffer1 <= 0;
buffer2 <= 0;
end
else begin
buffer1 <= data;
buffer2 <= buffer1;
end
end
reg rego;
always@(posedge clkb or negedge rst_n) begin
if(!rst_n)
rego <= 0;
else
rego <= buffer2;
end
assign sig_b = rego ^ buffer2;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 100ps/100ps
module pulse_detect(
input clka ,
input clkb ,
input rst_n ,
input sig_a ,
output sig_b
);
reg [1:0] cnt;
reg a;
always@(posedge clka or negedge rst_n)
begin if(!rst_n)
cnt <= 2'd0;
else if(cnt == 2'd2)
cnt <= 2'd0;
else if(a == 1'b1)
cnt <= cnt + 1'b1;
end
always@(posedge clka or negedge rst_n)
begin if(!rst_n)
a <=1'b0;
else if(sig_a)
a <=1'b1;
else if(cnt == 2'd2)
a <=1'b0;
end
//assign sig_b <= a;
reg sig_b1;
reg sig_b2;
always@(posedge clkb or negedge rst_n)
begin if(!rst_n)begin
sig_b1 <=1'b0;
sig_b2 <=1'b0;
end
else begin
sig_b1 <= a;
sig_b2 <= sig_b1;
end
end
assign sig_b = sig_b2;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 100ps/100ps
module pulse_detect(
input clka ,
input clkb ,
input rst_n ,
input sig_a ,
output sig_b
);
reg Q_sig_a;
always@(posedge clka or negedge rst_n)begin
if(~rst_n)begin
Q_sig_a<=0;
end
else if(sig_a)
Q_sig_a<=~Q_sig_a;
else
Q_sig_a<=Q_sig_a;
end
reg Q_buff0;
reg Q_buff1;
always @(posedge clkb or negedge rst_n) begin
if(~rst_n) begin
Q_buff0 <= 'd0;
Q_buff1 <= 'd0;
end
else begin
Q_buff0 <= Q_sig_a;
Q_buff1 <= Q_buff0;
end
end
reg Q_slow;
always @(posedge clkb or negedge rst_n) begin
if(~rst_n) begin
Q_slow <= 'd0;
end
else begin
Q_slow <= Q_buff1;
end
end
assign sig_b = Q_buff1 ^ Q_slow;
endmodule