VL70. 序列检测器（Moore型）
描述
请用Moore型状态机实现序列“1101”从左至右的不重叠检测。电路的接口如下图所示。当检测到“1101”，Y输出一个时钟周期的高电平脉冲。
接口电路图如下：
输入描述
input clk ,input rst_n ,
input din ,
输出描述
output reg YVL70. 序列检测器（Moore型）
描述
请用Moore型状态机实现序列“1101”从左至右的不重叠检测。输入描述
input clk ,输出描述
output reg YVerilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module det_moore(
input clk ,
input rst_n ,
input din ,
output reg Y
);
parameter s0=0,s1=1,s2=2,s3=3;
reg [1:0]state,next_state;
reg Yr;
always@(*)begin
case(state)
s0:next_state<=din?s1:s0;
s1:next_state<=din?s2:s0;
s2:next_state<=din?s1:s3;
s3:next_state<=s0;
endcase
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
state<=s0;
Y<=0;
Yr<=0;
end
else begin
state<=next_state;
Yr<=(state==s3)?din:0;
Y<=Yr;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module det_moore(
input clk ,
input rst_n ,
input din ,
output reg Y
);
parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
parameter S4 = 3'd4;
reg [3:0] cstate, nstate;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cstate <= S0;
end
else begin
cstate <= nstate;
end
end
always@(*) begin
case(cstate)
S0: begin
nstate = din?S1:S0;
end
S1: begin
nstate = din?S2:S0;
end
S2: begin
nstate = din?S2:S3;
end
S3: begin
nstate = din?S4:S0;
end
S4: begin
nstate = din?S1:S0;
end
endcase
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
Y <= 1'b0;
end
else begin
Y <= (cstate==S4);
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module det_moore(
input clk ,
input rst_n ,
input din ,
output reg Y
);
parameter s0 = 3'd0,
s1 = 3'd1,
s2 = 3'd2,
s3 = 3'd3,
s4 = 3'd4;
reg [2:0] cs,
ns;
always @(posedge clk or negedge rst_n)
cs <= (!rst_n) ? s0 : ns;
always @(*)
case(cs)
s0 : ns <= din ? s1 : s0;
s1 : ns <= din ? s2 : s0;
s2 : ns <= din ? s2 : s3;
s3 : ns <= din ? s4 : s0;
s4 : ns <= din ? s1 : s0;
default : ns <= s0;
endcase
always @(posedge clk or negedge rst_n)
if (!rst_n)
Y <= 1'b0;
else
case(cs)
s4 : Y<= 1'b1;
default : Y <= 1'b0;
endcase
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module det_moore(
input clk ,
input rst_n ,
input din ,
output reg Y
);
parameter idle = 0,
S1 = 1, S2 = 2, S3 = 3, S4 = 4;
reg[2:0] state, next_state;
always@(*)begin
case(state)
idle : next_state = din ? S1:idle;
S1 : next_state = din ? S2:idle;
S2 : next_state = (!din) ? S3:S2;
S3 : next_state = din ? S4:idle;
S4 : next_state = idle;
endcase
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)begin
Y <= 0;
end
else begin
if(state == S4)
Y <= 1;
else
Y <= 0;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)begin
state <= idle;
next_state <= idle;
end
else
state <= next_state;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module det_moore(
input clk ,
input rst_n ,
input din ,
output reg Y
);
parameter IDLE = 3'd0,
ST1 = 3'd1,
ST2 = 3'd2,
ST3 = 3'd3,
ST4 = 3'd4;
reg [2:0] state ,
next_state ;
always@(posedge clk or negedge rst_n)
if(!rst_n)
state <= IDLE;
else
state <= next_state;
always@(*)
case(state)
IDLE : next_state = (din) ? ST1 : IDLE; // 1/0
ST1 : next_state = (din) ? ST2 : IDLE; // 11/10
ST2 : next_state = (din) ? ST2 : ST3; // 111/110
ST3 : next_state = (din) ? ST4 : IDLE; // 1101/1100
ST4 : next_state = (din) ? ST1 : IDLE; // 11011/11010
default : next_state = IDLE;
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
Y <= 0;
else if(state == ST4)
Y <= 1'b1;
else
Y <= 1'b0;
endmodule