Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output reg clk_out
);
//*************code***********//
    reg sel1, sel0;
     
    always @ (negedge clk0, negedge rst) begin
        if(!rst)
            sel1 <= 0;
        else
            sel1 <= sel & ~sel0;
    end
     
    always @ (negedge clk1, negedge rst) begin
        if(!rst)
            sel0 <= 0;
        else
            sel0 <= ~sel & ~sel1;
    end 
     
    always @ (*) begin
        clk_out <= (sel1 & clk1) | (sel0 & clk0);
    end
//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output reg clk_out
);
//*************code***********//
reg s0_r;//clk0下降沿控制
reg s1_r;//clk1下降沿控制
assign s0 = !s1_r && !sel;//clk1手信号&&sel
assign s1 = !s0_r && sel;//clk0握手信号&&!sel
    
    always @(negedge clk0 or negedge rst)begin
        if(!rst)begin
            s1_r <= 1'b0;
        end
        else begin
            s1_r <= s1;
        end
    end
    always @(negedge clk1 or negedge rst)begin
        if(!rst)begin
            s0_r <= 1'b0;
        end
        else begin
            s0_r <= s0;
        end
    end
     always @ (*) begin
         clk_out <= (clk0 & s0_r)|(clk1 & s1_r);  
    end 

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output reg clk_out
);
//*************code***********//

    //sel为1 切换快时钟clk1
    reg sel1,sel0;
    always @(negedge clk0 or negedge rst) begin
       if(rst == 1'b0) 
           sel1 <= 0;
       else 
           sel1 <= !sel0 & sel;
    end

    always @(negedge clk1 or negedge rst) begin
       if(rst == 1'b0) 
           sel0 <= 0;
       else 
           sel0 <= !sel1 & !sel;
    end

    always@(*)begin
        clk_out <= (sel1 & clk1) | (sel0 & clk0);
    end

    

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output reg clk_out
);

    reg sel1, sel0;
     
    always @ (negedge clk0, negedge rst) begin
        if(!rst)
            sel1 <= 0;
        else
            sel1 <= sel & ~sel0;
    end
     
    always @ (negedge clk1, negedge rst) begin
        if(!rst)
            sel0 <= 0;
        else
            sel0 <= ~sel & ~sel1;
    end 
     
    always @ (*) begin
        clk_out <= (sel1 & clk1) | (sel0 & clk0);
    end



//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output  clk_out
);
//*************code***********//
  reg r_out0;
    reg r_out1;
    reg out0;
    reg out1;

    always @(negedge clk1 or negedge rst) begin
        if(!rst)
        r_out0<=0;
        else
        r_out0<=~sel&~r_out1;
    end

    always @(negedge clk0 or negedge rst) begin
        if(!rst)
        r_out1<=0;
        else
         r_out1<=sel&~r_out0;
    end


  assign clk_out=(r_out0&clk0)|(r_out1&clk1);


//*************code***********//
endmodule