Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
    reg[1:0] cnt;
    always@(posedge clk or negedge rst)
        if(!rst)
            cnt <= 0;
        else
            cnt <= cnt+1;
    always@(*)
        clk_out = cnt==1;
//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
parameter s0 = 4'b0001;
parameter s1 = 4'b0010;
parameter s2 = 4'b0100;
parameter s3 = 4'b1000;
    reg [3:0] cur_state;
    reg [3:0] next_state;
    always @(posedge clk or negedge rst)begin
        if(!rst)begin
            cur_state <= s0; 
        end
        else begin
            cur_state <= next_state;
        end
    end
    always @(*)begin
        case(cur_state)
            s0: next_state = s1;
            s1: next_state = s2;
            s2: next_state = s3;
            s3: next_state = s0;
            default : next_state = s0;
        endcase
    end
     always @(posedge clk or negedge rst)begin
        if(!rst)begin
            clk_out <= 1'b0; 
        end
        else begin
            case(cur_state)
                s0: clk_out <= 1'b1;
                s1: clk_out <= 1'b0;
                s2: clk_out <= 1'b0;
                s3: clk_out <= 1'b0;
            endcase
        end
    end

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
    reg [2:0]state,next_state;
    always@(*)begin
        case(state)
            s0:begin 
                next_state<=s1;
                clk_out<=0;
            end
            s1:begin 
                next_state<=s2;
                clk_out<=1;
            end
            s2:begin 
                next_state<=s3;
                clk_out<=0;
            end
            s3:begin 
                next_state<=s4;
                clk_out<=0;
            end
            s4:begin 
                next_state<=s1;
                clk_out<=0;
            end
        endcase
    end
    always@(posedge clk or negedge rst)begin
        if(~rst)
            state<=s0;
        else
            state<=next_state;
    end

            

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);
parameter IDLE = 0,s1= 1,s2= 2,s3=3;
    reg[2:0] st,nt;
//*************code***********//
    always@(posedge clk or negedge rst) begin
        if(!rst)
            st <= 'd0;
        else
            st <= nt;
    end
    
    always@(*) begin
        nt = IDLE;
        case(st)
            IDLE: nt = s1;
            s1: nt = s2;
            s2: nt = s3;
            s3: nt = IDLE;
            default :nt = IDLE;
        endcase
    end
    
    always@(posedge clk or negedge rst) begin
        if(!rst)
            clk_out<='d0;
        else
            clk_out <= (st==IDLE);
    end
    

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);
    parameter S0 = 2'b00;
    parameter S1 = 2'b01;
    parameter S2 = 2'b11;
    parameter S3 = 2'b10;
//*************code***********//
    reg [1:0] cstate, nstate;
    always@(posedge clk or negedge rst) begin
        if(!rst) begin
            cstate <= 2'd0;
        end
        else begin
            cstate <= nstate;
        end
    end
    
    always@(*) begin
        case(cstate)
            S0: begin
                nstate = S1;
            end
            S1: begin
                nstate = S2;
            end
            S2: begin
                nstate = S3;
            end
            S3: begin
                nstate = S0;
            end
            default: begin
                nstate = S0;
            end
        endcase
    end
    
    always@(posedge clk or negedge rst) begin
        if(!rst) begin
            clk_out <= 1'b0;
        end
        else begin
            clk_out = (cstate==S0);
        end
    end

//*************code***********//
endmodule