Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module game_count
(
input rst_n, //异位复位信号，低电平有效
input clk, //时钟信号
input [9:0]money,
input set,
input boost,
output reg[9:0]remain,
output reg yellow,
output reg red
);
//充值
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
remain <= 10'b0;
end
else begin
if(set) begin
remain <= remain + money;
end
else if(boost) begin
if(remain >= 10'd2) begin
remain <= remain - 2'd2;
end
end
else begin
if(remain >= 10'd1) begin
remain <= remain - 1'b1;
end
end
end
end
// 黄、红灯
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
yellow <= 1'b0;
red <= 1'b0;
end
else begin
if(remain > 10'd0 && remain < 10'd10) begin
yellow <= 1'b1;
end
else begin
yellow <= 1'b0;
end
if(remain == 10'd0) begin
red <= 1'b1;
end
else begin
red <= 1'b0;
end
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module game_count
(
input rst_n, //异位复位信号，低电平有效
input clk, //时钟信号
input [9:0]money,
input set,
input boost,
output reg[9:0]remain,
output reg yellow,
output reg red
);
parameter idle = 2'b0;
parameter normal = 2'b01;
parameter happy = 2'b10;
reg[9:0] cnt;
reg [1:0] state,next_state;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
remain <= 10'b0;
else
if (set)
remain <= money + remain;
else if (!boost)
remain <= (remain < 1)? remain:remain -1'b1;
else if (boost)
remain <= (remain <2)? remain:remain - 2'b10;
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
state <= 2'b0;
next_state <= 2'b0;
end
else
begin
state <= next_state;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
yellow <= 1'b0;
red <= 1'b0;
end
else
begin
yellow <= (remain <=10 && remain > 0)? 1'b1:1'b0;
red <= (state == normal && remain == 0)? 1'b1:
(state == happy && remain <2)? 1'b1:
(state == idle)? 1'b1:1'b0;
end
end
always @(*)
begin
case (state)
idle: next_state = (remain >= 0)? normal : idle;
normal : next_state = (boost == 1 )? happy:
(boost == 0 && remain >0)? normal:idle;
happy : next_state = (boost == 0 && remain >=1)? normal:
(boost == 1 && remain >=2)? happy:idle;
default next_state = idle;
endcase
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module game_count
(
input rst_n, //异位复位信号，低电平有效
input clk, //时钟信号
input [9:0]money,
input set,
input boost,
output reg[9:0]remain,
output reg yellow,
output reg red
);
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
yellow <= 0;
red <= 0;
end
else begin
yellow <= remain<10&&remain;
red <= boost? remain<2: remain<1;
end
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
remain <= 0;
else if(boost)
remain <= set ? remain+money:
remain<2? remain:
remain-2;
else
remain <= set ? remain+money:
remain<1? remain:
remain-1;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module game_count
(
input rst_n, //异位复位信号，低电平有效
input clk, //时钟信号
input [9:0]money,
input set,
input boost,
output reg[9:0]remain,
output reg yellow,
output reg red
);
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
remain<='d0;
else begin
if(set)begin
remain<=remain+money;
end
else begin
case(boost)
1'd1:remain<=remain-2'd2;
1'd0:remain<=remain-2'd1;
default:remain<=remain-2'd1;
endcase
end
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
red<='d0;
yellow<='d0;
end
else begin
yellow <= remain<10&&remain;
red <= boost? remain<2: remain<1;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module game_count
(
input rst_n, //异位复位信号，低电平有效
input clk, //时钟信号
input [9:0]money,
input set,
input boost,
output reg[9:0]remain,
output reg yellow,
output reg red
);
// reg mode;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
remain <= 0;
end
else if(set)
begin
remain <= boost?remain+money:remain+money;// 如果充值时也计费，这里就前面-2后面-1.现在更简洁的当然是直接写成remain+money咯
end
else
begin
remain <= boost?(remain<2?remain:remain-2):
(remain<1?remain:remain-1);
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
yellow <= 0;
red <= 0;
end
else
begin
yellow <= remain<10&&remain>0;
red <= boost?remain<2:remain<1;
end
end
endmodule
