Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

reg data_in_reg;
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		data_in_reg <= 0;
	else
		data_in_reg <= data_in;
end 

reg data_out_reg;
always @(*)
begin
	data_out_reg = data_in & ~data_in_reg;
end 

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		data_out <= 'b0;
	else 
		data_out <= data_out_reg;
end 

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
reg d1;
    always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
                begin
                    d1<='b0;
                    data_out='b0;
                end
            else
                begin 
                    d1<=data_in;
                    data_out<=data_in&(~d1);
                end
        end
                
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
reg        data_in_reg   ;
wire       data_out_reg0 ;
    always @(posedge clk or negedge rst_n)
        if(~rst_n)
            data_in_reg <= 1'b0;
        else
            data_in_reg <= data_in;
    assign data_out_reg0 = ~data_in_reg & data_in ;
    always @(posedge clk or negedge rst_n)
        if(~rst_n)
             data_out <= 1'b0;
         else 
             data_out <= data_out_reg0 ;
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

    reg q1;
    
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            q1       <=1'b0;
            data_out <=1'b0;
        end
        else begin
            q1      <=data_in;
            data_out<=(~q1)&data_in;
        end
    end
        
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
    wire a;
    reg d;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            d<=1'b0;
            data_out<=1'b0;
        end
        else begin
            d<=data_in;
            data_out<=a;
        end
    end
    assign a=data_in & (~d);
        

endmodule