Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
    
    reg      [3:0]   number_reg        ;
    always@(posedge clk or negedge rst_n)   
        begin
            if(rst_n==1'd0)
              number_reg <=4'd0            ;
            else if(set==1'd1)
              number_reg<= set_num         ;
            else 
              number_reg<=  number_reg + 1'd1  ;  
            
        end  
  always@(posedge clk or negedge rst_n)   
        begin
            if(rst_n==1'd0)
              number <=4'd0            ;
            else 
              number<=  number_reg         ;              
        end 
                
    always@(*)
        begin
           if(rst_n==1'd0)
              zero <= 1'd0          ;
            else if(number==4'd0)
               zero <= 1'd1         ; 
            else 
                zero <= 1'd0        ; 
        end
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
    
    reg [3:0] num;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            num<=0;
        else if(set)
            num<=set_num;
        else 
            num<=num+1'b1;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            zero<=0;
        else if(num==0)
            zero<=1;
        else
            zero<=0;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            number<=0;
        else
            number<=num;
    end
   
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
    
    reg    [3:0]    number_reg;
    
    always@(*) begin
        if(!rst_n)
            zero = 1'b0;
        else if(number == 4'd0)
            zero = 1'b1;
        else
            zero = 1'b0;        
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            number_reg    <= 4'd0;
        else if(set)
            number_reg    <= set_num;
        else
            number_reg    <= number_reg + 1'b1;        
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            number    <= 4'd0;
        else
            number    <= number_reg;        
    end
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
    
    reg [3:0] num_reg;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            num_reg <= 4'd0;
            zero <= 1'b0;
        end
        else begin
            if(set) begin
                num_reg <= set_num;
            end
            else begin
                num_reg <= num_reg + 1'b1;
            end
            
            zero <= (num_reg==4'd0)? 1'b1: 1'b0;
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            number <= 4'd0;
        end
        else begin
            number <= num_reg;
        end
    end
    
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
reg [3:0] number_reg;

always @(posedge clk or negedge rst_n) 
begin
   if(!rst_n)
     number_reg<=0;
   else if(set)
     number_reg<=set_num;
   else if(number_reg==4'hF)
     number_reg<=0;
   else 
     number_reg<=number_reg+1;
end

always @(posedge clk or negedge rst_n) 
   if(!rst_n)
     number<=0;
   else 
     number<=number_reg;

always @(posedge clk or negedge rst_n) 
   if(!rst_n)
     zero<=0;
   else if(number_reg==0)
     zero<=1;
   else 
     zero<=0;

endmodule