VL52. 加减计数器
描述
请编写一个十进制计数器模块，当mode信号为1，计数器输出信号递增，当mode信号为0，计数器输出信号递减。每次到达0，给出指示信号zero。
输入描述
输出描述
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module count_module(
input clk,
input rst_n,
input mode,
output reg [3:0]number,
output reg zero
);
reg [3:0] number_reg;
reg zero_reg;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
number_reg <= 4'd0;
else if(number_reg == 4'd9 & mode)
number_reg <= 4'd0;
else if(mode)
number_reg <= number_reg + 1'b1;
else if(!mode)
if(number_reg == 4'd0)
number_reg <= 4'd9;
else
number_reg <= number_reg - 1'b1;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
number <= 4'd0;
else
number <= number_reg;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
zero <= 1'b0;
else
zero <= number_reg == 4'd0;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module count_module(
input clk,
input rst_n,
input mode,
output reg [3:0]number,
output reg zero
);
reg [3:0]num;
always @(posedge clk or negedge rst_n )
begin
if(!rst_n)
num<=0;
else if(mode==1)
if(num==9)
num<=0;
else
num<=num+1;
else if(mode==0)
if(num==0)
num<=9;
else
num<=num-1;
end
always @(posedge clk or negedge rst_n )
if(!rst_n)
zero<=0;
else if(num==0)
zero<=1;
else
zero<=0;
always @(posedge clk or negedge rst_n )
if(!rst_n)
number<=0;
else
number<=num;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module count_module(
input clk,
input rst_n,
input mode,
output reg [3:0]number,
output reg zero
);
reg [3:0] num_tmp;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
num_tmp <= 4'd0;
end
else begin
if(mode) begin
if(num_tmp == 4'd9) begin
num_tmp <= 4'd0;
end
else begin
num_tmp <= num_tmp + 1'b1;
end
end
else begin
if(num_tmp == 4'd0) begin
num_tmp <= 4'd9;
end
else begin
num_tmp <= num_tmp - 1'b1;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
zero <= 1'b0;
end
else begin
zero <= (num_tmp==4'd0);
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
zero <= 1'b0;
end
else begin
zero <= (num_tmp==4'd0);
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
number <= 4'd0;
end
else begin
number <= num_tmp;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module count_module(
input clk,
input rst_n,
input mode,
output reg [3:0]number,
output reg zero
);
reg [3:0]num;
always@(posedge clk or negedge rst_n)
if(!rst_n)
num<=0;
else if(mode==1)begin
if(num==9)
num<=0;
else num<=num+1;
end
else if(mode==0)begin
if(num==0)
num<=9;
else num<=num-1;
end
else num<=num;
always@(posedge clk or negedge rst_n)
if(!rst_n)
zero<=0;
else if(num==0)
zero<=1;
else zero<=0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
number<=0;
else number<=num;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module count_module(
input clk,
input rst_n,
input mode,
output reg [3:0]number,
output reg zero
);
reg [3:0] num;
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
number<=0;
num<=0; end
else if(mode==1)
begin
num <= num==9 ? 0 : num+1 ;
number <= num;
end
else begin
num <= num==0 ? 9 :num-1;
number <= num;end
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
zero<=0;
end
else
zero<= num==0 ? 1 : 0;
end
endmodule