Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
	
    
    reg            time_vaild    ;
    always@(posedge clk or negedge rst_n)
        begin
            if(rst_n==1'd0)
               second <= 6'd0                     ;
            else if((time_vaild == 1'd1)&&(second == 6'd60))
                second <= 6'd1                    ; 
            else if(time_vaild == 1'd1)
                 second <=   second + 1'd1        ;    
            else
                 second <=   second               ;    
        end     
	
    always@(posedge clk or negedge rst_n)
        begin
            if(rst_n==1'd0)
               minute <= 6'd0                     ;
           else if(second == 6'd60)
                minute <=   minute   +1'd1        ;    
            else 
                 minute <=   minute               ;      
        end   
    always@(posedge clk or negedge rst_n)
        begin
            if(rst_n==1'd0)
               time_vaild <= 1'd1                 ;
           else if(( minute == 6'd59)&&(second == 6'd60))
                time_vaild <= 1'd0                ;
            else 
                 time_vaild <=   time_vaild       ;      
        end   
    
	
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
	
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            second    <= 6'd0;
            minute    <= 6'd0;
        end
        else if(minute < 6'd60) begin
            if(second == 60) begin
                second    <= 6'd1;
                minute    <= minute + 1'b1;
            end
            else begin
                second    <= second + 1'b1;
                minute    <= minute;
            end
        end
        else if(minute == 6'd60) begin
                second    <= 6'd0;
                minute    <= minute;
        end
    end
    
    
	
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            second <= 6'd0;
            minute <= 6'd0;
        end
        else begin
            if(minute == 6'd60) begin
                second <= 6'd0;
                minute <= minute;
            end
            else begin
                if(second == 6'd60) begin
                    second <= 6'd1;
                    minute <= minute + 1'b1;
                end
                else begin
                    second <= second + 1'b1;
                end
            end
        end
    end
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);    
always@(posedge clk or negedge rst_n)
   if(rst_n==0)
     second<=6'd0;
   else if(minute==60)
     second<=6'd0;
   else if(second==60)
     second<=1;
   else 
     second<=second+1;

always@(posedge clk or negedge rst_n)
   if(rst_n==0)
     minute<=6'd0;
   else if(minute==60)
     minute<=minute;
   else if(second==60)
     minute<=minute+1;




	
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            second<=0;
    else if(second==60)
        second<=1;
    else if(minute==60)
        second<=0;
    else second<=second+1;
   always@(posedge clk or negedge rst_n)
       if(!rst_n)
           minute<=0;
    else if(second==60)
        minute<=minute+1;
    else minute<=minute;
endmodule