VL27. 不重叠序列检测
描述
请编写一个序列检测模块，检测输入信号（a）是否满足011100序列， 要求以每六个输入为一组，不检测重复序列，例如第一位数据不符合，则不考虑后五位。一直到第七位数据即下一组信号的第一位开始检测。当信号满足该序列，给出指示信号match。当不满足时给出指示信号not_match。
模块的时序图如下：
请使用Verilog HDL实现以上功能，要求使用状态机实现，画出状态转化图。并编写testbench验证模块的功能。
输入描述
输出描述
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
parameter flag= 6'b011100;
reg[5:0]a;
reg [2:0] cnt;
reg b;
always@(posedge clk or negedge rst_n)
if(rst_n == 1'b0)
cnt <= 3'd0;
else if(cnt == 3'd5)
cnt <= 3'd0;
else
cnt <= cnt + 1'b1;
always@( posedge clk or negedge rst_n)
if(rst_n == 1'b0)
a <= 6'd0;
else
a <= {a[4:0],data};
always@( posedge clk or negedge rst_n)
if(rst_n == 1'b0)
b <= 1'b0;
else if(cnt == 3'd5)
b <= 1'b1;
else
b <= 1'b1;
always@( *)
if(b == 1'b1 && cnt == 3'd0)
begin
if(a == flag)
begin
match <= 1'b1;
not_match <= 1'b0;
end
else
begin
match <= 1'b0;
not_match <= 1'b1;
end
end
else
begin
match <= 1'b0;
not_match <= 1'b0;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
reg [5:0] seq;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
seq <= 'b0;
end else begin
seq <= {seq[4:0], data};
end
end
reg [2:0] count;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
count <= 'b0;
end else begin
count <= (count == 'd5) ? 'b0 : (count + 1'b1);
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
match <= 'b0;
not_match <= 'b0;
end else begin
match <= (count == 'd5) && ({seq[4:0], data} == 6'b011100);
not_match <= (count == 'd5) && ({seq[4:0], data} != 6'b011100);
end
end
// always@(*) begin
// match = (count == 'd5) && ({seq[4:0], data} == 6'b011100);
// not_match = (count == 'd5) && ({seq[4:0], data} != 6'b011100);
// end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
localparam S0 = 3'd0;
localparam S1 = 3'd1;
localparam S2 = 3'd2;
localparam S3 = 3'd3;
localparam S4 = 3'd4;
localparam S5 = 3'd6;
localparam S6 = 3'd7;
reg[2:0] state;
reg[2:0] cnt;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
cnt <= 3'd0;
else if(cnt == 3'd5)
cnt <= 3'd0;
else
cnt <= cnt + 1'b1;
end
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
state <= S0;
match <= 1'b0;
not_match <= 1'b0;
end
else
begin
case(state)
S0:
begin
if(data == 1'b1)
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S6;
end
else
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S1;
end
end
S1:
begin
if(data == 1'b0)
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S6;
end
else
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S2;
end
end
S2:
begin
if(data == 1'b0)
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S6;
end
else
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S3;
end
end
S3:
begin
if(data == 1'b0)
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S6;
end
else
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S4;
end
end
S4:
begin
if(data == 1'b1)
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S6;
end
else
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S5;
end
end
S5:
begin
if(data == 1'b1)
begin
not_match <= 1'b1;
match <= 1'b0;
state <= S0;
end
else
begin
not_match <= 1'b0;
match <= 1'b1;
state <= S0;
end
end
S6:
begin
if(cnt == 3'd5)
begin
not_match <= 1'b1;
match <= 1'b0;
state <= S0;
end
else
begin
not_match <= 1'b0;
match <= 1'b0;
state <= S6;
end
end
default: ;
endcase
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
parameter s_idle = 4'b0000;
parameter s1 = 4'b0001;
parameter s2 = 4'b0010;
parameter s3 = 4'b0011;
parameter s4 = 4'b0100;
parameter s5 = 4'b0101;
parameter s6 = 4'b0110;
parameter c1 = 4'b0111;
parameter c2 = 4'b1000;
parameter c3 = 4'b1001;
parameter c4 = 4'b1010;
parameter c5 = 4'b1011;
parameter c6 = 4'b1100;
reg [3:0] state;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= s_idle;
end
else begin
case(state)
s_idle : state <= ~data ? s1 : c1;
s1 : state <= data ? s2 : c2;
s2 : state <= data ? s3 : c3;
s3 : state <= data ? s4 : c4;
s4 : state <= ~data ? s5 : c5;
s5 : state <= ~data ? s6 : c6;
s6 : state <= ~data ? s1 : c1;
c1 : state <= c2;
c2 : state <= c3;
c3 : state <= c4;
c4 : state <= c5;
c5 : state <= c6;
c6 : state <= data ? c1 : s1;
default: state <= s_idle;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
match <= 0;
end
else begin
match <= ((state == s5) && ~data) ? 1 : 0;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
not_match <= 0;
end
else begin
not_match <= (state == c5) ? 1 : 0;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
parameter ZERO=0, ONE=1, TWO=2, THREE=3, FOUR=4, FIVE=5, SIX=6, SEVEN=7;
reg [2:0] state, nstate;
reg [2:0] cnt;
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
cnt <= 0;
else if(cnt == 6)
cnt <= 1;
else
cnt <= cnt + 1;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
state <= ZERO;
else
state <= nstate;
end
always@(*) begin
case(state)
ZERO : nstate = data ? SEVEN: ONE;
ONE : nstate = data ? TWO : SEVEN;
TWO : nstate = data ? THREE: SEVEN;
THREE : nstate = data ? FOUR : SEVEN;
FOUR : nstate = data ? SEVEN: FIVE;
FIVE : nstate = data ? SEVEN: SIX;
SIX : nstate = data ? SEVEN: ONE;
SEVEN : nstate = cnt == 6 && data == 0 ? ONE : SEVEN;
default: nstate = ZERO ;
endcase
end
always@(*) begin
if(~rst_n)
begin
match = 0;
not_match = 0;
end
else
begin
match = cnt == 6 && state == SIX;
not_match = cnt == 6 && nstate == SEVEN;
end
end
endmodule