VL28. 输入序列连续的序列检测
描述
题目描述：
请编写一个序列检测模块，输入信号端口为data，表示数据有效的指示信号端口为data_valid。当data_valid信号为高时，表示此刻的输入信号data有效，参与序列检测；当data_valid为低时，data无效，抛弃该时刻的输入。当输入序列的有效信号满足0110时，拉高序列匹配信号match。
模块的接口信号图如下：
模块的时序图如下：
请使用状态机实现以上功能，画出状态转移图并使用Verilog HDL编写代码实现以上功能，并编写testbench验证模块的功能.
输入描述
输出描述
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
reg [3:0] seq;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
seq <= 'b0;
end else begin
seq <= data_valid ? {seq[2:0], data} : 'b0;
end
end
always@(*) begin
match = seq == 4'b0110;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
parameter s_idle = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
reg [2:0] state;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= s_idle;
end
else if(data_valid) begin
case(state)
s_idle: state <= data ? s_idle : s1;
s1: state <= data ? s2 : s1;
s2: state <= data ? s3 : s1;
s3: state <= data ? s_idle : s4;
s4: state <= data ? s_idle : s1;
default: state <= s_idle;
endcase
end
else begin
state <= state;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
match <= 0;
end
else begin
match <= (state == s3 && !data && data_valid) ? 1 : 0;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
reg[3:0] data_reg;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
data_reg <= 4'd0;
else if(data_valid == 1'b1)
data_reg <= {data_reg[2:0], data};
else
data_reg <= 4'd0;
end
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
match <= 1'b0;
else if({data_reg[2:0], data} == 4'b0110)
match <= 1'b1;
else
match <= 1'b0;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
reg [3:0] shift_reg;
reg match_reg;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
shift_reg <= 4'd0;
else if(data_valid)
shift_reg <= {data, shift_reg[3:1]};
else
shift_reg <= shift_reg;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
match_reg <= 1'b0;
else if(shift_reg == 4'b0110)
match_reg <= 1'b1;
else
match_reg <= 1'b0;
end
always @(*) begin
if(shift_reg == 4'b0110 && match_reg == 1'b0)
match = 1'b1;
else
match = 1'b0;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
reg[3:0]reg_data;
always@(posedge clk or negedge rst_n)
if(~rst_n)
reg_data<=4'd0;
else if(data_valid)
reg_data<={reg_data[2:0],data};
else
reg_data<=reg_data;
always@(posedge clk or negedge rst_n)
if(~rst_n)
match<=0;
else if(reg_data[2:0]==3'b011 & data==0)
match<=1;
else
match<=0;
endmodule