VL26. 含有无关项的序列检测
描述
请编写一个序列检测模块，检测输入信号a是否满足011XXX110序列（长度为9位数据，前三位是011，后三位是110，中间三位不做要求），当信号满足该序列，给出指示信号match。
程序的功能时序图如下：
请使用Verilog HDL实现以上功能，并编写testbench验证模块的功能。 要求代码简洁，功能完整。
输入描述
输出描述
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg [3:0] cnt;
reg [8:0] data_r;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt <= 4'd0;
else if(cnt==4'd8)
cnt <= 4'd0;
else
cnt <= cnt+1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
data_r <= 9'd0;
else
data_r <= {data_r[7:0],a};
always@(posedge clk or negedge rst_n)
if(!rst_n)
match <= 1'b0;
else
match <= (data_r[8:6]==3'b011 && data_r[2:0]==3'b110);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg[8:0] data;
always@(posedge clk or negedge rst_n)
if(rst_n == 1'b0)
data <= 9'd0;
else
data<={data[7:0],a};
always@(posedge clk or negedge rst_n)
if (rst_n == 1'b0)
match <= 1'b0;
else if(data[8:6] == 3'b011 && data[2:0] == 3'b110)
match<=1'b1;
else
match<=1'b0;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg [8:0] seq;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
seq <= 'b0;
end else begin
seq <= {seq[7:0], a};
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
match <= 'b0;
end else begin
casex(seq)
9'b0_11xx_x110: match <= 1'b1;
default: match <= 1'b0;
endcase
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg [8:0]sequence;
always@(posedge clk or negedge rst_n)
if(!rst_n)
sequence <= 0;
else
sequence <= {sequence[7:0],a};
always@(posedge clk or negedge rst_n)
if(!rst_n)
match <= 0;
else if(sequence[8:6]==3'b011&&sequence[2:0]==3'b110)
match <= 1'b1;
else
match <= 0;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg[8:0] aa;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
match<=0;
else
casex (aa)
9'b011xxx110 : match <= 1'b1;
default : match <= 1'b0;
endcase
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
aa<=0;
else
aa<={aa[7:0],a};
end
endmodule