VL25. 输入序列连续的序列检测
描述
请编写一个序列检测模块，检测输入信号a是否满足01110001序列，当信号满足该序列，给出指示信号match。
模块的接口信号图如下：
模块的时序图如下：
请使用Verilog HDL实现以上功能，并编写testbench验证模块的功能
输入描述
clk：系统时钟信号
rst_n：异步复位信号，低电平有效
a：单比特信号，待检测的数据
输出描述
match：当输入信号a满足目标序列，该信号为1，其余时刻该信号为0
VL25. 输入序列连续的序列检测
描述
请编写一个序列检测模块，检测输入信号a是否满足01110001序列，当信号满足该序列，给出指示信号match。
模块的接口信号图如下：
模块的时序图如下：
输入描述
输出描述
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg [7:0] a_temp;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a_temp <= 8'd0;
match <= 0;
end
else begin
a_temp <= {a_temp[6:0],a};
if(a_temp == 8'b0111_0001) match <= 1;
else match <=0;
end
end
/*reg [7:0] A, B;
reg [3:0] cnt;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
match <= 0;
cnt <= 0;
A <= 8'd0;
B <= 8'b0111_0001;
end
else begin
case(cnt)
4'd0: begin
A[7] <= a;
cnt <= cnt + 1'b1;
end
4'd1: begin
A[6] <= a;
cnt <= cnt + 1'b1;
end
4'd2: begin
A[5] <= a;
cnt <= cnt + 1'b1;
end
4'd3: begin
A[4] <= a;
cnt <= cnt + 1'b1;
end
4'd4: begin
A[3] <= a;
cnt <= cnt + 1'b1;
end
4'd5: begin
A[2] <= a;
cnt <= cnt + 1'b1;
end
4'd6: begin
A[1] <= a;
cnt <= cnt + 1'b1;
end
4'd7: begin
A[0] <= a;
cnt <= cnt + 1'b1;
end
4'd8:begin
if(A===B) begin
match <= 1;
end
else begin
match <= 0;
A <= {A[6:0],a};
end
end
default: begin
cnt <= 0;
A <=0;
end
endcase
end
end*/
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
parameter s_0 = 4'b0000;
parameter s_1 = 4'b0001;
parameter s_2 = 4'b0010;
parameter s_3 = 4'b0011;
parameter s_4 = 4'b0100;
parameter s_5 = 4'b0101;
parameter s_6 = 4'b0110;
parameter s_7 = 4'b0111;
parameter s_8 = 4'b1000;
reg [3:0]cstate,nstate;
always@(posedge clk,negedge rst_n)
begin
if(!rst_n)
begin
cstate <= s_0;
end
else
begin
cstate <= nstate;
end
end
always@(*)
begin
case(cstate)
s_0:begin if(a == 1'b0) nstate = s_1; else nstate = s_0;end
s_1:begin if(a == 1'b1) nstate = s_2; else nstate = s_1;end
s_2:begin if(a == 1'b1) nstate = s_3; else nstate = s_1;end
s_3:begin if(a == 1'b1) nstate = s_4; else nstate = s_1;end
s_4:begin if(a == 1'b0) nstate = s_5; else nstate = s_0;end
s_5:begin if(a == 1'b0) nstate = s_6; else nstate = s_2;end
s_6:begin if(a == 1'b0) nstate = s_7; else nstate = s_2;end
s_7:begin if(a == 1'b1) nstate = s_8; else nstate = s_1;end
s_8:begin if(a == 1'b0) nstate = s_1; else nstate = s_3;end
default:nstate = s_0;
endcase
end
always@(posedge clk, negedge rst_n)
begin
if(!rst_n)
match <= 1'b0;
else
match <= cstate == s_8;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
parameter IDLE = 9'b0_0000_0001;
parameter S1 = 9'b0_0000_0010;
parameter S2 = 9'b0_0000_0100;
parameter S3 = 9'b0_0000_1000;
parameter S4 = 9'b0_0001_0000;
parameter S5 = 9'b0_0010_0000;
parameter S6 = 9'b0_0100_0000;
parameter S7 = 9'b0_1000_0000;
parameter S8 = 9'b1_0000_0000;
reg [8:0] state,n_state;
always@(posedge clk or negedge rst_n)
if(!rst_n)
state <= IDLE;
else
state <= n_state;
always@(*)
if(!rst_n)
n_state <= IDLE;
else
case(state)
IDLE: n_state <= a?IDLE:S1;
S1: n_state <= a?S2:S1;
S2: n_state <= a?S3:S1;
S3: n_state <= a?S4:S1;
S4: n_state <= a?IDLE:S5;
S5: n_state <= a?IDLE:S6;
S6: n_state <= a?IDLE:S7;
S7: n_state <= a?S8:S1;
S8: n_state <= a?IDLE:S1;
default: n_state <= IDLE;
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
match <= 1'b0;
else if(state==S8)
match <= 1'b1;
else
match <= 1'b0;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg[7:0] data;
always@(posedge clk or negedge rst_n)
if(rst_n == 1'b0)
data <= 8'd0;
else
data<={data[6:0],a};
always@(posedge clk or negedge rst_n)
if (rst_n == 1'b0)
match <= 1'b0;
else if(data == 8'b01110001)
match<=1'b1;
else
match<=1'b0;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg [7:0]sequence;
parameter A = 8'b01110001;
always@(posedge clk or negedge rst_n)
if(!rst_n)
sequence <= 0;
else
sequence <= {sequence[6:0],a};
always@(posedge clk or negedge rst_n)
if(!rst_n)
match <= 0;
else if(sequence==A)
match <= 1;
else
match <= 0;
endmodule