Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
    reg [3:0] MEM [0:7];
    //read
    always@(posedge clk,negedge rst_n)begin
        if(~rst_n)
            read_data <= 0;
        else if(read_en)
            read_data <= MEM[read_addr];
        else
            read_data <= 0;
    end
    //write
    integer i;
    always@(posedge clk,negedge rst_n)begin
        if(~rst_n)begin
            for(i=0;i<7;i=i+1)begin
                MEM[i] <= 0;
            end
        end
        else if(write_en)
            MEM[write_addr] <= write_data;
    end

	
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
    
    reg [3:0] mem [7:0];
    
    genvar i;
    generate for(i = 0; i < 8; i = i + 1)begin : ram
        always @(posedge clk or negedge rst_n)begin
            if(!rst_n)begin
                mem[i] <= 4'b0;
            end
            else if(write_en)
                mem[write_addr] <= write_data;
            else
                mem[write_addr] <= mem[write_addr];
        end
    end
    endgenerate
    
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            read_data <= 4'b0;
        end
        else if(read_en)
            read_data <= mem[read_addr];
        else
            read_data <= 4'b0;
    end
        
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
	
    reg    [3:0]    mem[7:0];
    integer i;
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            for(i=0;i<8;i=i+1)
                mem[i]    <= 4'd0;
        else if(write_en)
            mem[write_addr]    <= write_data;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            read_data    <= 4'd0;
        else if(read_en)
            read_data    <=  mem[read_addr];
    end
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
reg [3:0] buffer [7:0];
genvar i;
    generate for ( i=0 ;i<8 ;i=i+1 )
begin
always @(posedge clk or negedge rst_n)
      if(!rst_n)
         buffer[i]<=0;
      else if(write_en==1) 
         buffer[write_addr]<=write_data;
      else 
          buffer[write_addr]<=buffer[write_addr];
end
endgenerate 

always @(posedge clk or negedge rst_n)
      if(!rst_n)
        read_data<=4'd0;
    else if(read_en==1)
        read_data<=buffer[read_addr];
      else 
        read_data<=read_data;



endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
    reg [3:0] ram_reg[7:0];//定义RAM
    integer i;
    always@(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
            for(i = 0; i < 8; i= i+1)begin
                ram_reg[i] <= 4'b0;
            end
        end
        else begin
         if(write_en)begin
                ram_reg[write_addr] <= write_data;
            end
            else begin
                ram_reg[write_addr] <= ram_reg[write_addr];
            end
        end
    end
    

    //读操作
    reg [3:0] rd_data;
    always@(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
            read_data <= 8'b0;
        end
        else begin
            if(read_en)begin
                read_data <= ram_reg[read_addr];
            end
            else begin
                read_data<= read_data;
            end
        end
    end
    
    
endmodule