Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
            Q<=4'd0;
        else
            Q<={~Q[0],Q[3:1]};
    end
        
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            Q <= 4'b0;
        end
        else
            Q <= {~Q[0], Q[3:1]};
    end
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
    
    reg    [3:0]    q,Q_d;

    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            Q <= 4'd0;
        else
            Q <= {!Q[0],Q[3:1]};
    end
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
always @(posedge clk or negedge rst_n) 
begin
   if(rst_n==0)
     Q<=4'd0;
   else 
     Q<={~Q[0],Q[3:1]};
end



endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
    reg [3:0] next;
    
    always @(*) begin
        next = {~Q[0], Q[3:1]};
    end
    
    always @(posedge clk or negedge rst_n) begin
        if(~rst_n)
            Q <= 4'd0;
        else
            Q <= next;
    end
endmodule