Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
    reg a_tmp;
    always @ (posedge clk or negedge rst_n) begin
        if (!rst_n)
            a_tmp <= 1'b0;
        else
            a_tmp <= a;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            rise <= 1'b0;
            down <= 1'b0;
        end
        else if ((!a_tmp)&a) begin
            rise <= 1'b1;
            down <= 1'b0;
        end
        else if ((!a)&a_tmp) begin
            rise <= 1'b0;
            down <= 1'b1;
        end
        else begin
            rise <= 1'b0;
            down <= 1'b0;
        end
    end
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
    reg q;
    always@(posedge clk or negedge rst_n)begin 
        if(!rst_n) begin rise <= 0; down <= 0; q<=0;end
        else  q<=a;
        rise <=  ((a & ~q)===1)?1:0;  
        down <=  ((~a & q)===1)?1:0;  
    end
  endmodule   

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	
    reg a0;
    reg a1;
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            a0 <= 1'b0;
            a1 <= 1'b0;
        end else begin
            a0 <= a;
            a1 <= a0;
        end
    end
    
//     always@(posedge clk or negedge rst_n) begin
//         if(!rst_n) begin
//             rise <= 1'b0;
//             down <= 1'b0;
//         end else begin
//             a_beater <= a;
//         end
//     end
    
    always@(*) begin
        rise = (~a1 & a0) === 1;
        down = (a1 & ~a0) === 1;
    end
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	
    //寄存上一拍a的值
    reg a_tmp;
    always@(posedge clk or negedge rst_n)begin
        if(~rst_n) a_tmp <= 0;
        else a_tmp <= a;
    end
    
    always@(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
            rise <= 0;
            down <=0;
        end
        else begin
            if(~a_tmp && a)begin
               rise <= 1;
               down <= 0;
            end
            else if(a_tmp && ~a)begin
                rise <= 0;
                down <= 1;
            end
            else begin
                rise <= 0;
                down <= 0;
            end
        end
    end
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	reg a0, a1;
    wire rise1, down1;
    //reg flag_rise, flag_down;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            rise <= 0;
            down <= 0;
            a0 <=0;
            a1 <=0;
           end
        else begin
            a0 <= a;
            if(a>a0) begin rise <= 1; down <= 0; end
            else if(a<a0) begin down <= 1; rise <= 0; end
            else begin 
                rise <= 0;
                down <=0;
            end
            //a1 <= a0;
            //rise <= a & (~a0);
           // down <= a0 & (~a);
            /*if(flag_rise) rise <=1;
            if(flag_down) down <= 1;
            else begin
                rise <=0;
                down <=0;
            end*/
        end
    end
    //assign rise1 = a0 & (~a1);
    //assign down1 = a1 & (~a0);
    
endmodule