Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module function_mod(
	input [3:0]a,
	input [3:0]b,
	input clk,rst_n,
	output [3:0]c,
	output [3:0]d
);
    function [3:0] rev(input [3:0] data);
        integer i;
        for(i = 0;i < 4;i=i+1)
             rev[i] = data[3-i];
    endfunction
    
    assign c = rev(a);
    assign d = rev(b);
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module function_mod(
    input clk,
    input rst_n,
	input [3:0]a,
	input [3:0]b,
	
	output [3:0]c,
	output [3:0]d
);
    function [3:0] data_rev;
        input [3:0] a;
        data_rev = {a[0],a[1],a[2] ,a[3]};
    endfunction
    assign c = data_rev(a);
    assign d = data_rev(b);
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module function_mod(
	input [3:0]a,
	input [3:0]b,
    input clk,
    input rst_n,
	
	output [3:0]c,
	output [3:0]d
);
    reg[3:0] c;
    reg[3:0] d;
    always@( clk or negedge rst_n)
        if(~rst_n)
            begin
             c<=0;
             d<=0;
             end
    else begin
        c<=inv(a);
        d<=inv(b);
        
    end

    function[3:0] inv;
        input[3:0] e;
     
        integer i; 
        
            for(i=0; i<4; i=i+1)
          begin 
              inv[i]=e[3-i];
        end
    endfunction
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module function_mod(
	input clk,
    input rst_n,
    input [3:0]a,
	input [3:0]b,
	
	output [3:0]c,
	output [3:0]d
);

    function [3:0] begin_end;
    input [3:0] data_in;
    begin
        begin_end[0] = data_in[3];
        begin_end[1] = data_in[2];
        begin_end[2] = data_in[1];
        begin_end[3] = data_in[0];
    end 
endfunction

assign c = begin_end(a);
assign d = begin_end(b);
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module function_mod(
    input clk,
    input rst_n,
	input [3:0]a,
	input [3:0]b,
	
	output [3:0]c,
	output [3:0]d
);

    assign c = data_rev(a);
    assign d = data_rev(b);
    
    function [3:0] data_rev;
        input [3:0] data_in;
        begin
            data_rev[0] = data_in[3];
            data_rev[1] = data_in[2];
            data_rev[2] = data_in[1];
            data_rev[3] = data_in[0];
        end
    endfunction
endmodule