Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module comparator_4(
	input		[3:0]       A   	,
	input	   [3:0]		B   	,
 
 	output	 wire		Y2    , //A>B
	output   wire        Y1    , //A=B
    output   wire        Y0      //A<B
);
    assign Y2 = (A[3]>B[3]) | ((A[3]==B[3]) & (A[2]>B[2])) | ((A[3]==B[3]) & (A[2]==B[2]) & (A[1]>B[1])) |((A[3]==B[3]) & (A[2]==B[2]) & (A[1]==B[1]) & (A[0]>B[0]));
    assign Y1 = (A[3]==B[3]) & (A[2]==B[2]) & (A[1]==B[1]) & (A[0]==B[0]);
    assign Y0 = (A[3]<B[3]) | ((A[3]==B[3]) & (A[2]<B[2])) | ((A[3]==B[3]) & (A[2]==B[2]) & (A[1]<B[1])) |((A[3]==B[3]) & (A[2]==B[2]) & (A[1]==B[1]) & (A[0]<B[0]));       
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module comparator_4(
    input        [3:0]       A       ,
    input       [3:0]        B       ,
 
     output     wire        Y2    , //A>B
    output   wire        Y1    , //A=B
    output   wire        Y0      //A<B
);

    
    
    
    assign Y2 = (A[3]>B[3])|((A[3]==B[3])&(A[2]>B[2]))|((A[3]==B[3])&(A[2]==B[2])&(A[1]>B[1]))|((A[3]==B[3])&(A[2]==B[2])&(A[1]==B[1])&(A[0]>B[0]));                       
    assign Y1 = (A[3]==B[3]) & (A[2]==B[2]) & (A[1]==B[1]) & (A[0]==B[0]);
    assign Y0 = (A[3]<B[3])|((A[3]==B[3])&(A[2]<B[2]))|((A[3]==B[3])&(A[2]==B[2])&(A[1]<B[1]))|((A[3]==B[3])&(A[2]==B[2])&(A[1]==B[1])&(A[0]<B[0]));                  
                                
                                
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module comparator_4(
	input		[3:0]       A   	,
	input	   [3:0]		B   	,
 
 	output	 wire		Y2    , //A>B
	output   wire        Y1    , //A=B
    output   wire        Y0      //A<B
);
    assign Y2 = A>B;
    assign Y1 = A==B;
    assign Y0 = A<B;
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module comparator_4(
	input		[3:0]       A   	,
	input	   [3:0]		B   	,
 
 	output	 wire		Y2    , //A>B
	output   wire        Y1    , //A=B
    output   wire        Y0      //A<B
);

wire W_y2[0:3];
wire W_y1[0:3];
wire W_y0[0:3];

genvar gen_i;
for (gen_i = 0; gen_i < 4; gen_i = gen_i + 1) begin
	compare_1 compare_1_u(
	.A (A[gen_i]   ),
    .B (B[gen_i]   ),
	.Y2(W_y2[gen_i]),//A>B
	.Y1(W_y1[gen_i]),//A=B
	.Y0(W_y0[gen_i]) //A<B
);
end

assign Y2 = W_y2[3] | ((W_y1[3]) & (W_y2[2])) | ((W_y1[3]) & (W_y1[2]) & (W_y2[1])) | ((W_y1[3]) & (W_y1[2]) & (W_y1[1]) & (W_y2[0]));
assign Y0 = W_y0[3] | ((W_y1[3]) & (W_y0[2])) | ((W_y1[3]) & (W_y1[2]) & (W_y0[1])) | ((W_y1[3]) & (W_y1[2]) & (W_y1[1]) & (W_y0[0]));
assign Y1 = W_y1[3] & W_y1[2] & W_y1[1] & W_y1[0];



endmodule 

module compare_1(
	input A,
	input B,
	output Y2,//A>B
	output Y1,//A=B
	output Y0 //A<B
);

assign Y2 = A & (!B);
assign Y0 = (!A) & B;
assign Y1 = !(Y2 | Y0);


endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module comparator_4(
	input		[3:0]       A   	,
	input	   [3:0]		B   	,
 
 	output	 wire		Y2    , //A>B
	output   wire        Y1    , //A=B
    output   wire        Y0      //A<B
);

    xnor xnr0(xnr0_o, A[0], B[0]),
    xnr1(xnr1_o, A[1], B[1]),
    xnr2(xn2_o, A[2], B[2]),
    xnr3(xn3_o, A[3], B[3]);
//     and and_y1(Y1, xnr0_o, xnr1_o, xnr2_o, xnr3_o);
    assign Y1 = (A==B);
    
    not nt0(nt0_o, A[0]),
    nt1(nt1_o, A[1]),
    nt2(nt2_o, A[2]),
    nt3(nt3_o, A[3]),
    nt4(nt4_o, B[0]),
    nt5(nt5_o, B[1]),
    nt6(nt6_o, B[2]),
    nt7(nt7_o, B[3]);
    
    and ad0(ad0_o, A[0], nt4_o),
    ad1(ad1_o, A[1], nt5_o),
    ad2(ad2_o, A[2], nt6_o),
    ad3(ad3_o, A[3], nt7_o),
    ad4(ad4_o, xn3_o, ad2_o),
    ad5(ad5_o, xn3_o, xn2_o, ad1_o),
    ad6(ad6_o, xn3_o, xn2_o, xn1_o, ad0_o);
    or or0(Y2, ad3_o, ad4_o, ad5_o, ad6_o);
    
    and ad7(ad7_o, nt0_o, B[0]),
    ad8(ad8_o, nt1_o, B[1]),
    ad9(ad9_o, nt2_o, B[2]),
    ad10(ad10_o, nt3_o, B[3]),
    ad11(ad11_o, xn3_o, ad9_o),
    ad12(ad12_o, xn3_o, xn2_o, ad8_o),
    ad13(ad13_o, xn3_o, xn2_o, xn1_o, ad7_o);
    or or1(Y0, ad10_o, ad11_o, ad12_o, ad13_o);
endmodule