VL38. 自动贩售机1
描述
题目描述：
设计一个自动贩售机，输入货币有三种，为0.5/1/2元，饮料价格是1.5元，要求进行找零，找零只会支付0.5元。
ps:
投入的货币会自动经过边沿检测并输出一个在时钟上升沿到1，在下降沿到0的脉冲信号
注意rst为低电平复位
信号示意图：
d1 0.5元
d2 1元
d3 2元
out1 饮料
out2 零钱
输入描述
输入信号 clk rst d1 d2 d3输出描述
输出信号 out1 [1:0]out2Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//*************code***********//
parameter a=3'd0,b=3'd1,c=3'd2,d=3'd3,e=3'd4,f=3'd5,g=3'd6;
reg[2:0]state;
always@(posedge clk or negedge rst)begin
if(!rst)
state<=a;
else begin
case(state)
a:state<=d1?b:
d2?c:
d3?d:a;
b:state<=d1?c:
d2?e:
d3?f:b;
c:state<=d1?e:
d2?d:
d3?g:c;
d:state<=a;
e:state<=a;
f:state<=a;
g:state<=a;
default:state<=a;
endcase
end
end
always@(posedge clk or negedge rst)begin
if(!rst)
out1<=1'b0;
else
out1<=state==d||state==e||state==g||state==f;
end
always@(posedge clk or negedge rst)begin
if(!rst)
out2<=2'd0;
else if(state==d)
out2<=2'd1;
else if(state==f)
out2<=2'd2;
else if(state==g)
out2<=2'd3;
else
out2<=2'b0;
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//*************code***********//
parameter s0 = 'd0; // 0
parameter s1 = 'd1; // 0.5
parameter s2 = 'd2; // 1
parameter s3 = 'd3; // 1.5
parameter s4 = 'd4; // 2
parameter s5 = 'd5; // 2.5
parameter s6 = 'd6; // 3
reg [2:0] state, nstate;
wire [2:0] input_state;
assign input_state = {d1, d2, d3};
always@(posedge clk or negedge rst) begin
if(~rst)
state <= s0;
else
state <= nstate;
end
always@(*) begin
case(state)
s0:begin
case(input_state)
3'b100:nstate = s1; //0.5
3'b010:nstate = s2; // 1
3'b001:nstate = s4; // 2
default:nstate = nstate;
endcase
end
s1:begin
case(input_state)
3'b100:nstate = s2;
3'b010:nstate = s3;
3'b001:nstate = s5;
default:nstate = nstate;
endcase
end
s2:begin
case(input_state)
3'b100:nstate = s3;
3'b010:nstate = s4;
3'b001:nstate = s6;
default:nstate = nstate;
endcase
end
default: nstate = s0;
endcase
end
always@(posedge clk or negedge rst) begin
if(~rst) begin
out1 <= 'd0;
out2 <= 'd0;
end
else begin
case(nstate)
s3: begin
out1 <= 1'b1;
out2 <= 2'b0;
end
s4: begin
out1 <= 1'b1;
out2 <= 2'b1;
end
s5: begin
out1 <= 1'b1;
out2 <= 2'b10;
end
s6: begin
out1 <= 1'b1;
out2 <= 2'b11;
end
default: begin
out1 <= 1'b0;
out2 <= 2'b0;
end
endcase
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//*************code***********//
reg [3:0] cnt;
always@(posedge clk or negedge rst)begin
if(!rst)begin
cnt <= 0;
out1 <= 0;
out2 <= 0;
end
else begin
if(d1) cnt <= cnt + 1;
else if(d2) cnt <= cnt + 2;
else if(d3) cnt <= cnt + 4;
else if(cnt >= 3)begin
out1 <= 1;
out2 <= cnt - 3;
cnt <= 0;
end
else begin
out1 <= 0;
out2 <= 0;
end
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 , //0.5
input wire d2 , //1
input wire d3 , //2
output reg out1,
output reg [1:0]out2 // 00 01 10 11
);
//*************code***********//
parameter IDLE = 7'b0000001;
parameter S0 = 7'b0000010;
parameter S1 = 7'b0000100;
parameter S2 = 7'b0001000;
parameter S3 = 7'b0010000;
parameter S4 = 7'b0100000;
parameter S5 = 7'b1000000;
//1，第一段 当前状态
reg[6:0] cs,ns;
always @(posedge clk or negedge rst)begin
if(~rst) cs <= IDLE;
else cs <= ns;
end
//2.第二段 状态跳转
always @(*)begin
if(~rst) ns = IDLE;
else begin
case(cs)
IDLE:begin
if(d1) ns = S0;
else if(d2) ns = S1;
else if(d3) ns = S3;
else ns = ns;
end
S0:begin
if(d1)ns = S1;
else if(d2) ns = S2;
else if(d3)ns = S4;
else ns = ns;
end
S1:begin
if(d1) ns = S2;
else if(d2) ns = S3;
else if(d3) ns = S5;
else ns = ns;
end
default: ns = IDLE;
endcase
end
end
//3.第三段 状态输出
always @(posedge clk or negedge rst)begin
if(~rst)begin
out1 <= 0;
out2 <= 2'b0;
end
else begin
case(ns)
S2:begin
out1 <= 1;
out2 <= 2'b00;
end
S3:begin
out1 <= 1;
out2 <= 2'b01;
end
S4:begin
out1 <= 1;
out2 <= 2'b10;
end
S5:begin
out1 <= 1;
out2 <= 2'b11;
end
default begin
out1 <= 0;
out2 <= 2'b00;
end
endcase
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//*************code***********//
parameter
S0 = 'd0,
S1 = 'd1,
S2 = 'd2,
S3 = 'd3,
S4 = 'd4,
S5 = 'd5,
S6 = 'd6;
reg [2:0] curr_state, next_state;
wire [2:0] input_state;
assign input_state = {d3, d2, d1};
always @(posedge clk or negedge rst)
begin
if(~rst)
curr_state <= 'd0;
else
curr_state <= next_state;
end
always @(*)
begin
if(~rst)
next_state = 'd0;
else
case(curr_state)
S0:
begin
case(input_state)
3'b001: next_state = S1;
3'b010: next_state = S2;
3'b100: next_state = S4;
default: next_state = next_state;
endcase
end
S1:
begin
case(input_state)
3'b001: next_state = S2;
3'b010: next_state = S3;
3'b100: next_state = S5;
default: next_state = next_state;
endcase
end
S2:
begin
case(input_state)
3'b001: next_state = S3;
3'b010: next_state = S4;
3'b100: next_state = S6;
default: next_state = next_state;
endcase
end
default:
next_state <= S0;
endcase
end
always @(posedge clk or negedge rst)
begin
if(~rst)
begin
out1 <= 'd0;
out2 <= 'd0;
end
else
begin
case(next_state)
// S0:
// begin
// out1 <= 'd0;
// out2 <= 'd0;
// end
// S1:
// begin
// out1 <= 'd0;
// out2 <= 'd1;
// end
// S2:
// begin
// out1 <= 'd0;
// out2 <= 'd2;
// end
S3:
begin
out1 <= 'd1;
out2 <= 'd0;
end
S4:
begin
out1 <= 'd1;
out2 <= 'd1;
end
S5:
begin
out1 <= 'd1;
out2 <= 'd2;
end
S6:
begin
out1 <= 'd1;
out2 <= 'd3;
end
default:
begin
out1 <= 'd0;
out2 <= 'd0;
end
endcase
end
end
//*************code***********//
endmodule