VL39. 自动贩售机2
描述
题目描述：
设计一个自动贩售机，输入货币有两种，为0.5/1元，饮料价格是1.5/2.5元，要求进行找零，找零只会支付0.5元。
ps:
1、投入的货币会自动经过边沿检测并输出一个在时钟上升沿到1，在下降沿到0的脉冲信号
2、此题忽略出饮料后才能切换饮料的问题
注意rst为低电平复位
信号示意图：
d1 0.5
d2 1
sel 选择饮料
out1 饮料1
out2 饮料2
输入描述
输入信号 clk rst d1 d2 sel输出描述
输出信号 out1 out2 out3Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire sel ,
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
parameter a=3'd0,b=3'd1,c=3'd2,d=3'd3,e=3'd4,f=3'd5,g=3'd6;
reg[2:0]state;
always@(posedge clk or negedge rst)begin
if(!rst)
state<=a;
else
case(state)
a:state<=d1?c:
d2?b:a;
b:state<=d1?e:
d2?d:b;
c:state<=d1?b:
d2?e:c;
d:state<=(sel==1'b0)?a:
d1?f:
d2?g:d;
e:state<=(sel==1'b0)?a:
d1?d:
d2?f:e;
f:state<=a;
g:state<=a;
default:state<=a;
endcase
end
always@(posedge clk or negedge rst)begin
if(!rst)
out1<=1'b0;
else if(sel==1'b0)
out1<=(state==e)||(state==d);
else
out1<=1'b0;
end
always@(posedge clk or negedge rst)begin
if(!rst)
out2<=1'b0;
else if(sel==1'b1)
out2<=state==f||state==g;
else
out2<=1'b0;
end
always@(posedge clk or negedge rst)begin
if(!rst)
out3<=1'b0;
else if(sel==1'b0)
out3<=(state==d);
else if(sel==1'b1)
out3<=(state==g);
else
out3<=1'b0;
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire sel ,
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5,s6=3'd6;
reg [2:0] state,next_state;
always@(posedge clk or negedge rst) begin
if(!rst)
state<=s0;
else
state<=next_state;
end
always@(*) begin
if(!sel) begin
case(state)
s0:begin
if(d1)
next_state=s1;
else if(d2)
next_state=s2;
else
next_state=next_state;
end
s1:begin
if(d1)
next_state=s2;
else if(d2)
next_state=s3;
else
next_state=next_state;
end
s2:begin
if(d1)
next_state=s3;
else if(d2)
next_state=s4;
else
next_state=next_state;
end
s3:next_state=s0;
s4:next_state=s0;
default:next_state=s0;
endcase
end
else begin
case(state)
s0:begin
if(d1)
next_state=s1;
else if(d2)
next_state=s2;
else
next_state=next_state;
end
s1:begin
if(d1)
next_state=s2;
else if(d2)
next_state=s3;
else
next_state=next_state;
end
s2:begin
if(d1)
next_state=s3;
else if(d2)
next_state=s4;
else
next_state=next_state;
end
s3:begin
if(d1)
next_state=s4;
else if(d2)
next_state=s5;
else
next_state=next_state;
end
s4:begin
if(d1)
next_state=s5;
else if(d2)
next_state=s6;
else
next_state=next_state;
end
s5:next_state=s0;
s6:next_state=s0;
default:next_state=s0;
endcase
end
end
always@(posedge clk or negedge rst) begin
if(!rst)
{out1,out2,out3}=3'b000;
else if(!sel) begin
case(next_state)
s3:{out1,out2,out3}=3'b100;
s4:{out1,out2,out3}=3'b101;
default:{out1,out2,out3}=3'b000;
endcase
end
else begin
case(next_state)
s5:{out1,out2,out3}=3'b010;
s6:{out1,out2,out3}=3'b011;
default:{out1,out2,out3}=3'b000;
endcase
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire sel ,
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
parameter S0 = 'd0, S1 = 'd1, S2 = 'd2, S3 = 'd3 , S4 = 'd4, S5 = 'd5, S6 = 'd6;
reg [2:0] current_state;
reg [2:0] next_state;
wire [1:0] input_state;
assign input_state = {d1,d2};
always@(posedge clk or negedge rst)begin
if(rst == 1'b0)begin
current_state <= S0;
end
else begin
current_state <= next_state;
end
end
always@(*)begin
if (!sel) begin
case(current_state)
S0:begin
case(input_state)
2'b10 :next_state = S1 ;
2'b01 :next_state = S2 ;
default:next_state = next_state;
endcase
end
S1:begin
case(input_state)
2'b10 :next_state = S2 ;
2'b01 :next_state = S3 ;
default:next_state = next_state;
endcase
end
S2:begin
case(input_state)
2'b10 :next_state = S3 ;
2'b01 :next_state = S4 ;
default:next_state = next_state;
endcase
end
default: next_state = S0;
endcase
end
else begin
case(current_state)
S0:begin
case(input_state)
2'b10 :next_state = S1 ;
2'b01 :next_state = S2 ;
default:next_state = next_state;
endcase
end
S1:begin
case(input_state)
2'b10 :next_state = S2 ;
2'b01 :next_state = S3 ;
default:next_state = next_state;
endcase
end
S2:begin
case(input_state)
2'b10 :next_state = S3 ;
2'b01 :next_state = S4 ;
default:next_state = next_state;
endcase
end
S3:begin
case(input_state)
2'b10 :next_state = S4 ;
2'b01 :next_state = S5 ;
default:next_state = next_state;
endcase
end
S4:begin
case(input_state)
2'b10 :next_state = S5 ;
2'b01 :next_state = S6 ;
default:next_state = next_state;
endcase
end
default: next_state = S0;
endcase
end
end
always@(posedge clk or negedge rst)begin
if(rst == 1'b0)begin
out1 <= 1'b0;
out2 <= 1'b0;
out3 <= 1'b0;
end
else begin
if(!sel)begin
case (next_state)
S3: begin out1 <= 1'b1;out2 <= 1'b0;out3 <= 1'b0;end
S4: begin out1 <= 1'b1;out2 <= 1'b0;out3 <= 1'b1;end
default:begin out1 <= 1'b0;out2 <= 1'b0;out3 <= 1'b0;end
endcase
end
else begin
case (next_state)
S5: begin out1 <= 1'b0;out2 <= 1'b1;out3 <= 1'b0;end
S6: begin out1 <= 1'b0;out2 <= 1'b1;out3 <= 1'b1;end
default:begin out1 <= 1'b0;out2 <= 1'b0;out3 <= 1'b0;end
endcase
end
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 , // 0.5元
input wire d2 , // 1元
input wire sel , // 低为out1,高为out2
output reg out1, // 1.5元一瓶
output reg out2, // 2.5元一瓶
output reg out3 // 零钱
);
//*************code***********//
reg [2:0] cnt;
always @(posedge clk or negedge rst) begin
if(!rst) begin
cnt <= 3'd0;
end
else begin
if((sel && cnt >= 3'd5) || (!sel && cnt >= 3'd3)) begin
cnt <= 3'd0;
end
else if(d1) begin
cnt <= cnt + 1'b1;
end
else if(d2) begin
cnt <= cnt + 2'b10;
end
end
end
always @(posedge clk or negedge rst) begin
if(!rst) begin
out1 <= 1'b0;
out2 <= 1'b0;
out3 <= 1'b0;
end
else begin
if(!sel) begin
if(cnt >= 3'd3) begin
out1 <= 1'b1;
out3 <= cnt - 2'd3;
end
else begin
out1 <= 1'b0;
out3 <= 1'b0;
end
end
else begin // sel==1
if(cnt >= 3'd5) begin
out2 <= 1'b1;
out3 <= cnt - 3'd5;
end
else begin
out2 <= 1'b0;
out3 <= 1'b0;
end
end
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire sel ,
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
reg [3:0] coin;
reg d1_d,d2_d;
always@(*) begin
d1_d = d1;
d2_d = d2;
end
always@(negedge clk or negedge rst) begin
if(!rst)
coin <= 4'd0;
else if(!sel) begin
if(coin >= 2'd3)
coin <= coin - 2'd3;
else if(d1_d)
coin <= coin + 1'b1;
else if(d2_d)
coin <= coin + 2'd2;
else
coin <= coin;
end
else if(sel) begin
if(coin >= 3'd5)
coin <= coin - 3'd5;
else if(d1_d)
coin <= coin + 1'b1;
else if(d2_d)
coin <= coin + 2'd2;
else
coin <= coin;
end
end
always@(posedge clk or negedge rst) begin
if(!rst) begin
out1 <= 1'b0;
out2 <= 1'b0;
end
else if(!sel & (coin >= 3'd3))begin
out1 <= 1'b1;
end
else if(sel & (coin >= 3'd5))begin
out2 <= 1'b1;
end
else begin
out1 <= 1'b0;
out2 <= 1'b0;
end
end
always@(posedge clk or negedge rst) begin
if(!rst) begin
out3 <= 1'b0;
end
else if(!sel & (coin >= 3'd3))begin
out3 <= coin - 3'd3;
end
else if(sel & (coin >= 3'd5))begin
out3 <= coin - 3'd5;
end
else begin
out3 <= 1'b0;
end
end
//*************code***********//
endmodule