Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//

    reg [2:0]cnt;
    always@(posedge clk_in or negedge rst)
        if(!rst)
            cnt <= 3'b011;
    else
        cnt <= cnt+1;
     
    assign clk_out2 = ~cnt[0];
    assign clk_out4 = ~cnt[1];
    assign clk_out8 = cnt[2];
//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
    reg div2,div4,div8;
    assign clk_out2 = div2;    
    assign clk_out4 = div4;   
    assign clk_out8 = div8;
    //2
    always @ (posedge clk_in or negedge rst)
        if(!rst)
            div2 <= 0;
        else div2 <= ~div2;
    //4
    always @ (posedge div2 or negedge rst)
        if(!rst)
            div4 <= 0;
    else div4 <= ~div4;
    //8
    always @ (posedge div4 or negedge rst)
        if(!rst)
            div8 <= 0;
        else div8 <= ~div8;


//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg [2:0] count;

    always @(posedge clk_in or negedge rst)begin
        if (~rst) begin
         count<= 3'd0;    
        end
        else begin 
           count<=count -3'd1;
        end

    end
    assign clk_out2=count[0] ;  
    assign clk_out4=count[1] ;   
    assign clk_out8=count[2] ;

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
    reg clk_2,clk_4,clk_8;
    always@(posedge clk_in or negedge rst)begin
        if(!rst)
            clk_2<=1'b0;
        else
            clk_2<=~clk_2;
    end
    always@(posedge clk_2 or negedge rst)begin
        if(!rst)
            clk_4<=1'b0;
        else
            clk_4<=~clk_4;
    end
    always@(posedge clk_4 or negedge rst)begin
        if(!rst)
            clk_8<=1'b0;
        else
            clk_8<=~clk_8;
    end
assign clk_out2=clk_2;
    assign clk_out4=clk_4;
    assign clk_out8=clk_8;
    
//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
    reg clk_out2_r, clk_out4_r, clk_out8_r;
    
    always@(posedge clk_in or negedge rst) begin
        if(~rst)
            clk_out2_r <= 0;
        else
            clk_out2_r <= ~clk_out2_r;
    end
    
    always@(posedge clk_out2 or negedge rst) begin
        if(~rst)
            clk_out4_r <= 0;
        else
            clk_out4_r <= ~clk_out4_r;
    end
    
    always@(posedge clk_out4 or negedge rst) begin
        if(~rst)
            clk_out8_r <= 0;
        else
            clk_out8_r <= ~clk_out8_r;
    end
    
    assign clk_out2 = clk_out2_r;
    assign clk_out4 = clk_out4_r;
    assign clk_out8 = clk_out8_r;

//*************code***********//
endmodule