VL36. 状态机-重叠序列检测
描述
设计一个状态机，用来检测序列 1011，要求：
1、进行重叠检测 即10110111 会被检测通过2次
2、寄存器输出，在序列检测完成下一拍输出检测有效
注意rst为低电平复位
信号示意图：
波形示意图：
输入描述
输入信号 clk rst data类型 wire
输出描述
输出信号 flag类型 reg
VL36. 状态机-重叠序列检测
描述
设计一个状态机，用来检测序列 1011，要求：
1、进行重叠检测 即10110111 会被检测通过2次
2、寄存器输出，在序列检测完成下一拍输出检测有效
注意rst为低电平复位
信号示意图：
输入描述
输入信号 clk rst data输出描述
输出信号 flagVerilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
/*
parameter s0 = 'd0 ;
parameter s1 = 'd1 ;
parameter s2 = 'd2 ;
parameter s3 = 'd3 ;
parameter s4 = 'd4 ;
// parameter s5 = 'd5 ;
reg [2:0] cs,ns ;
always @ (posedge clk or negedge rst) begin
if(!rst)
cs <= s0 ;
else
cs <= ns ;
end
always @ (posedge clk or negedge rst) begin
if(!rst)
flag <= 1'b0 ;
else //flag <= ns == s4 ;
if (ns == s4)
flag <= 1'b1 ;
else flag <= 1'b0 ; // flag <= ns == s5 ;
end // flag <= (ns == s5) ? 1 : 0 ;
always @ (*) begin
case (cs)
s0: if (data) ns = s1 ;
else ns = s0 ;
s1: if(!data) ns = s2 ;
else ns = s1 ;
s2: if(data) ns = s3 ;
else ns = s0 ;
s3: if(data) ns = s4 ;
else ns = s2 ;
s4: if(data) ns = s1 ;
else ns = s2 ;
default : ns = s0 ;
endcase
end
*/
parameter S0 = 'd0, S1 = 'd1, S2 = 'd2, S3 = 'd3 , S4 = 'd4;
reg [2:0] current_state;
reg [2:0] next_state;
always@(posedge clk or negedge rst)begin
if(rst == 1'b0)begin
current_state <= S0;
end
else begin
current_state <= next_state;
end
end
always@(*)begin
case(current_state)
S0:begin
next_state = data ? S1 : S0;
end
S1:begin
next_state = data? S1 : S2;
end
S2:begin
next_state = data ? S3 : S0;
end
S3:begin
next_state = data ? S4 : S2;
end
S4:begin
next_state = data ? S1 : S2;
end
default:begin
next_state = S0;
end
endcase
end
always@(posedge clk or negedge rst)begin
if(rst == 1'b0)begin
flag <= 1'b0;
end
else begin
if(current_state == S4)begin
flag <= 1'b1;
end
else begin
flag <= 1'b0;
end
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
parameter a=3'd0,b=3'd1,c=3'd2,d=3'd3,e=3'd4;
reg[2:0]state;
always@(posedge clk or negedge rst)begin
if(!rst)
state<=a;
else
case(state)
a:state<=data?b:a;
b:state<=data?b:c;
c:state<=data?d:a;
d:state<=data?e:c;
e:state<=data?b:c;
default:state<=a;
endcase
end
always@(posedge clk or negedge rst)begin
if(!rst)
flag<=1'b0;
else if(state==e)
flag<=1'b1;
else
flag<=1'b0;
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
parameter S0=0, S1=1, S2=2, S3=3, S4=4;
reg [2:0] state, nstate;
always@(posedge clk or negedge rst) begin
if(~rst)
state <= S0;
else
state <= nstate;
end
always@(*) begin
if(~rst)
nstate <= S0;
else
case(state)
S0 : nstate <= data? S1: S0;
S1 : nstate <= data? S1: S2;
S2 : nstate <= data? S3: S0;
S3 : nstate <= data? S4: S2;
S4 : nstate <= data? S1: S2;
default: nstate <= S0;
endcase
end
always@(posedge clk or negedge rst) begin
if(~rst)
flag <= 0;
else
flag <= state==S4;
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
parameter s0 = 3'd0;
parameter s1 = 3'd1;
parameter s2 = 3'd2;
parameter s3 = 3'd3;
parameter s4 = 3'd4;
reg [2:0] state, nstate;
always@(posedge clk or negedge rst) begin
if(~rst)
state <= s0;
else
state <= nstate;
end
always@(*) begin
if(~rst)
nstate <= s0;
else begin
case(state)
s0:nstate <= data?s1:s0;
s1:nstate <= data?s1:s2;
s2:nstate <= data?s3:s0;
s3:nstate <= data?s4:s2;
s4:nstate <= data?s1:s2;
default:nstate <= s0;
endcase
end
end
always@(posedge clk or negedge rst) begin
if(~rst)
flag <= 1'd0;
else
flag <= state == s4;
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
parameter S0=0, S1=1, S2=2, S3=3, S4=4;
reg [2:0] state, nstate;
always@(posedge clk or negedge rst) begin
if(~rst)
state <= S0;
else
state <= nstate;
end
always@(*) begin
if(~rst)
nstate = S0;
else
case(state)
S0 : nstate = data? S1: S0;
S1 : nstate = data? S1: S2;
S2 : nstate = data? S3: S0;
S3 : nstate = data? S4: S2;
S4 : nstate = data? S1: S2;
default: nstate = S0;
endcase
end
always@(posedge clk or negedge rst) begin
if(~rst)
flag <= 0;
else
flag <= state==S4;
end
//*************code***********//
endmodule