VL5. 位拆分与运算
描述
题目描述：
现在输入了一个压缩的16位数据，其实际上包含了四个数据[3:0][7:4][11:8][15:12],
现在请按照sel选择输出四个数据的相加结果,并输出valid_out信号（在不输出时候拉低）
0: 不输出且只有此时的输入有效
1：输出[3:0]+[7:4]
2：输出[3:0]+[11:8]
3：输出[3:0]+[15:12]
信号示意图：
输入描述
输出描述
输出信号 validout outVerilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,
output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0] d_vald;
always @ (posedge clk or negedge rst)begin
if(!rst)
d_vald <= 0;
else if(sel == 0)
d_vald <= d;
else
d_vald <= d_vald;
end
always @ (posedge clk or negedge rst)begin
if(!rst)begin
out <= 5'd0;
validout <= 0;
end
else
case(sel)
0:begin out <= 5'd0; validout <= 0; end
1:begin out <= d_vald[3:0] + d_vald[7:4]; validout <= 1; end
2:begin out <= d_vald[3:0] + d_vald[11:8]; validout <= 1; end
3:begin out <= d_vald[3:0] + d_vald[15:12]; validout <= 1; end
endcase
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,
output [4:0]out,
output validout
);
//*************code***********//
reg [15:0] d_reg;
reg [4:0] out;
reg validout;
always@(posedge clk or negedge rst) begin
if(!rst) begin
out<=0;
validout<=0;
end
else begin
case(sel)
2'b00: begin
out<=4'b0000;
d_reg<=d;
validout<=0;
end
2'b01: begin
out<=d_reg[3:0]+d_reg[7:4];
validout<=1;
end
2'b10: begin
out<=d_reg[3:0]+d_reg[11:8];
validout<=1;
end
2'b11: begin
out<=d_reg[3:0]+d_reg[15:12];
validout<=1;
end
endcase
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,
output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0]d1;
always@(posedge clk or negedge rst)
if(!rst) begin
validout<=1'b0;
out<=5'd0;
d1<=16'd0;
end
else begin
case(sel)
0:begin out<=5'd0;d1<=d; validout<=1'b0;end
1:begin out<=d1[3:0]+d1[7:4] ;validout<=1'b1;end
2:begin out<=d1[3:0]+d1[11:8] ;validout<=1'b1;end
3:begin out<=d1[3:0]+d1[15:12] ;validout<=1'b1;end
default:begin
validout<=1'b0;
out<=5'd0;
d1<=16'd0;
end
endcase
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,
output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0]data_lock;
always@(posedge clk or negedge rst) begin
if (!rst)
data_lock <= 0;
else if(!sel)
data_lock <= d;
end
always@(posedge clk or negedge rst)begin
if(!rst)begin
out<='b0;
validout <=0;
end
else begin
case (sel)
0:begin
out<='d0;
validout <=0;
end
1:begin
out<=data_lock[3:0]+data_lock[7:4];
validout <=1;
end
2:begin
out<=data_lock[3:0]+data_lock[11:8];
validout <=1;
end
3:begin
out<=data_lock[3:0]+data_lock[15:12];
validout <=1;
end
endcase
end
end
//*************code***********//
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,
output [4:0]out,
output validout
);
//*************code***********//
reg [4:0] out;
reg validout;
// reg [4:0] vld_data;
reg [15:0] vld_data;
always @(posedge clk or negedge rst) begin
if (! rst) begin
vld_data <= 16'b0;
end
else begin
if (sel == 0)
vld_data <= d;
else
vld_data <= vld_data;
end
end
always @(posedge clk or negedge rst) begin
if (! rst) begin
out <= 5'b0;
validout <= 1'b0;
end
else begin
case (sel)
2'b00: begin
validout <= 1'b0;
out <= 5'b0;
end
2'b01: begin
validout <= 1'b1;
out <= vld_data[3:0] + vld_data[7:4];
end
2'b10: begin
validout <= 1'b1;
out <= vld_data[3:0] + vld_data[11:8];
end
2'b11: begin
validout <= 1'b1;
out <= vld_data[3:0] + vld_data[15:12];
end
default: begin
validout <= 1'b0;
out <= 5'b0;
end
endcase
end
end
//*************code***********//
endmodule