VL6. 多功能数据处理器
描述
根据指示信号select的不同，对输入信号a,b实现不同的运算。输入信号a,b为8bit有符号数，当select信号为0，输出a；当select信号为1，输出b；当select信号为2，输出a+b；当select信号为3，输出a-b.
输入描述
输出描述
c：9bit位宽的有符号数Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_select(
input clk,
input rst_n,
input signed[7:0]a,
input signed[7:0]b,
input [1:0]select,
output reg signed [8:0]c
);
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
c<=9'b0;
end
else begin
case(select)
2'b00:begin
c<=a;
end
2'b01:begin
c<=b;
end
2'b10:begin
c<=a+b;
end
2'b11:begin
c<=a-b;
end
endcase
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_select(
input clk,
input rst_n,
input signed[7:0]a,
input signed[7:0]b,
input [1:0]select,
output reg signed [8:0]c
);
always@(posedge clk or negedge rst_n)
if(rst_n==1'b0)
c <= 9'b0;
else
case(select)
0: c <= a;
1: c <= b;
2: c <= a+b;
3: c <= a-b;
endcase
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_select(
input clk,
input rst_n,
input signed[7:0]a,
input signed[7:0]b,
input [1:0]select,
output reg signed [8:0]c
);
reg [7:0]data_a;
always@(posedge clk or negedge rst_n) begin
if (!rst_n)
data_a <= 0;
else if(!select)
data_a <= a;
end
reg [7:0]data_b;
always@(posedge clk or negedge rst_n) begin
if (!rst_n)
data_b <= 0;
else if(!select)
data_b <= b;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
c<='b0;
end
else begin
case (select)
0:begin
c<=a;
end
1:begin
c<=b;
end
2:begin
c<=a+b;
end
3:begin
c<=a-b;
end
endcase
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_select(
input clk,
input rst_n,
input signed[7:0]a,
input signed[7:0]b,
input [1:0]select,
output reg signed [8:0]c
);
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
c <= 9'd0;
else
case(select)
2'd0:c <= a;
2'd1:c <= b;
2'd2:c <= a+b;
2'd3:c <= a-b;
endcase
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module data_select(
input clk,
input rst_n,
input signed[7:0]a,
input signed[7:0]b,
input [1:0]select,
output reg signed [8:0]c
);
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
c <= 0;
else begin
case (select)
2'd0 : c <= a;
2'd1 : c <= b;
2'd2 : c <= a+b;
2'd3 : c <= a-b;
default : c <= 0;
endcase
end
end
endmodule