VL32. 非整数倍数据位宽转换24to128
描述
实现数据位宽转换电路，实现24bit数据输入转换为128bit数据输出。其中，先到的数据应置于输出的高bit位。
输入描述
input clk ,输出描述
output reg valid_out ,Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [3:0] cnt;
reg [127:0] data_lock;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<=0;
else if(valid_in)
cnt<=cnt+1'b1;
else
cnt<=cnt;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
data_lock<=0;
else if(valid_in)
data_lock<={data_lock[103:0],data_in};
else
data_lock<=data_lock;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
data_out<=0;
else if(cnt==5)
data_out<={data_lock[119:0],data_in[23:16]};
else if(cnt==10)
data_out<={data_lock[111:0],data_in[23:8]};
else if(cnt==15)
data_out<={data_lock[103:0],data_in};
else
data_out<=data_out;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
valid_out<=0;
else if(cnt==5)
valid_out<=1;
else if(cnt==10)
valid_out<=1;
else if(cnt==15)
valid_out<=1;
else
valid_out<=0;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [3:0] cnt;
reg [119:0] buffer;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 0;
buffer <= 0;
end
else if(valid_in) begin
buffer <= {buffer[95:0],data_in};
cnt <= (cnt == 4'b1111) ? 0 : cnt + 1;
end
else begin
cnt <= cnt;
buffer <= buffer;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out <= 0;
valid_out<= 0;
end
else if((cnt == 4'b0101) && valid_in) begin
data_out <= {buffer[119:0],data_in[23:16]};
valid_out<= 1;
end
else if((cnt == 4'b1010) && valid_in) begin
data_out <= {buffer[111:0],data_in[23:8]};
valid_out<= 1;
end
else if((cnt == 4'b1111) && valid_in) begin
data_out <= {buffer[103:0],data_in[23:0]};
valid_out<= 1;
end
else begin
data_out <= data_out;
valid_out<= 0;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg[3:0] cnt;
reg[127:0] data_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 4'b0;
end else if(valid_in) begin
cnt <= (cnt==4'd15)?'b0:cnt+1'b1;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_r <= 'b0;
end else begin
data_r <= (valid_in)?{data_r[103:0],data_in[23:0]}:data_r;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
valid_out <=1'b0;
end else begin
valid_out <=(valid_in)&(cnt==5 | cnt==10 | cnt==15)?1'b1:1'b0;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out <=128'b0;
end else if((cnt==5)&valid_in) begin
data_out <={data_r[119:0],data_in[7:0]};
end else if((cnt==10)&valid_in) begin
data_out <={data_r[111:0],data_in[15:0]};
end else if((cnt==15)&valid_in) begin
data_out <={data_r[103:0],data_in[23:0]};
end else begin
data_out <=data_out;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [3:0] cnt;
reg [127:0] data_lock;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt <= 'b0;
else if (valid_in)
cnt <= cnt +'b1;
else
cnt <= cnt;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
valid_out <= 'b0;
else begin
if(valid_in && (cnt == 4'd5 || cnt == 4'd10 || cnt == 4'd15))
valid_out <= 'b1;
else
valid_out <= 'b0;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_lock <= 'b0;
else if (valid_in)
data_lock <= {data_lock[103:0],data_in};
else
data_lock <= data_lock;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_out <= 0;
else if(valid_in && cnt == 4'd5)
data_out <= {data_lock[119:0],data_in[23:16]};
else if(valid_in && cnt == 4'd10)
data_out <= {data_lock[111:0],data_in[23:8]};
else if(valid_in && cnt == 4'd15)
data_out <= {data_lock[103:0],data_in};
else
data_out <= data_out;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [3:0] cnt;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<=0;
else if(valid_in)
cnt<=cnt+1;
end
reg [127:0] dbuf;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
valid_out<=0;
else if((cnt==5 || cnt==10 || cnt==15) && valid_in)
valid_out<=1;
else
valid_out<=0;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
dbuf<=0;
else if(valid_in) begin
dbuf<={dbuf[103:0],data_in};
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
data_out <= 0;
else if(valid_in) begin
case(cnt)
5:data_out<={dbuf[0+:120],data_in[23-:8]};
10:data_out<={dbuf[111:0],data_in[23-:16]};
15:data_out<={dbuf[103:0],data_in};
endcase
end
end
endmodule