VL33. 非整数倍数据位宽转换8to12
描述
实现数据位宽转换电路，实现8bit数据输入转换为12bit数据输出。其中，先到的数据应置于输出的高bit位。
输入描述
input clk ,输出描述
output reg valid_out,Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_8to12(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [11:0] data_out
);
reg [1:0] cnt;
reg [7:0] buffer;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 0;
buffer <= 0;
end
else if(valid_in) begin
buffer <= {buffer[7:0],data_in};
cnt <= (cnt == 2'b10) ? 0 : cnt + 1;
end
else begin
cnt <= cnt;
buffer <= buffer;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out <= 0;
valid_out<= 0;
end
else if((cnt == 2'b01) && valid_in) begin
data_out <= {buffer[7:0],data_in[7:4]};
valid_out<= 1;
end
else if((cnt == 2'b10) && valid_in) begin
data_out <= {buffer[3:0],data_in[7:0]};
valid_out<= 1;
end
else begin
data_out <= data_out;
valid_out<= 0;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_8to12(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [11:0] data_out
);
reg [1:0] cnt;
reg [7:0] data_lock;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<=0;
else if(valid_in) begin
if(cnt==2)
cnt<=0;
else
cnt<=cnt+1'b1;
end
else
cnt<=cnt;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
data_lock<=0;
else if(valid_in)
data_lock<=data_in;
else
data_lock<=data_lock;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out<=0;
valid_out<=1'b0;
end
else if(valid_in && cnt==1) begin
data_out<={data_lock,data_in[7:4]};
valid_out<=1'b1;
end
else if(valid_in && cnt==2) begin
data_out<={data_lock[3:0],data_in};
valid_out<=1'b1;
end
else begin
data_out<=data_out;
valid_out<=1'b0;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_8to12(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [11:0] data_out
);
reg [1:0] cnt;
reg [7:0] data_r;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 2'b0;
end else if(valid_in) begin
cnt <= (cnt=='d2)?2'b0:cnt+1'b1;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_r <= 8'b0;
end else if(valid_in) begin
data_r <= data_in;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
valid_out <= 1'b0;
end else if(valid_in)begin
valid_out <= cnt==2'b01 | cnt==2'b10;
end else begin
valid_out <= 1'b0; // 快速 归零，或者 报错，持续周期 过长了
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out <= 12'b0;
end else if((valid_in)&(cnt=='d1)) begin
data_out <= {data_r,data_in[7:4]};
end else if((valid_in)&(cnt=='d2)) begin
data_out <= {data_r[3:0],data_in};
end else begin
data_out <= data_out;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_8to12(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [11:0] data_out
);
reg [1:0] cnt;
reg [11:0] data_out_reg;
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
cnt<='d0;
else if(cnt=='d2&&valid_in)
cnt<='d0;
else if(valid_in)
cnt<=cnt+1;
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
data_out_reg<='d0;
else if(valid_in)
data_out_reg<={data_out_reg[3:0],data_in[7:0]};
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
valid_out<='d0;
else if(valid_in&&(cnt=='d1||cnt=='d2))
valid_out<='d1;
else
valid_out<='d0;
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
data_out<='d0;
else if(valid_in&&cnt=='d1)
data_out<={data_out_reg[7:0],data_in[7:4]};
else if(valid_in&&cnt=='d2)
data_out<={data_out_reg[3:0],data_in};
else
data_out<=data_out;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module width_8to12(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [11:0] data_out
);
reg [1:0] cnt ;
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
cnt <= 1'b0 ;
end
else if ( valid_in ) begin
cnt <= ( cnt == 2 ) ? 4'b0 : ( cnt + 1'b1) ;
end
end
//valid_out
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
valid_out <= 1'b0 ;
end
else if ( valid_in ) begin
valid_out <= ( cnt == 1 || cnt == 2 ) ? 1'b1 : 1'b0 ;
end
else valid_out <= 1'b0 ;
end
reg [7:0] data_lock ;
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
data_lock <= 0;
end if (valid_in) begin
data_lock <= data_in ;
end
end
// data_out
always @ ( posedge clk or negedge rst_n ) begin
if ( !rst_n ) begin
data_out <= 0 ;
end
else if (valid_in) begin
if ( cnt == 1 )
data_out <= { data_lock , data_in[7:4] } ;
else if ( cnt == 2 )
data_out <= { data_lock[3:0] , data_in } ;
end
end
endmodule