Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
    reg cnt;
    reg [7:0] data_r;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cnt <= 1'b0;
        end else begin
            cnt <= (valid_in)?cnt+1:cnt;
        end
    end
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            data_r <= 8'b0;
        end else begin
            data_r <= (valid_in)?data_in:data_r;
        end
    end
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            valid_out <= 1'b0;
        end else if(valid_in) begin
            valid_out <= (cnt==1);
        end else begin
            valid_out <= 1'b0;
        end
    end  
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            data_out <= 16'b0;
        end else if(valid_in) begin
            data_out <= (cnt==1)?{data_r,data_in}:data_out;
        end
    end 
    
        
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

/*实现数据位宽转换电路，实现8bit数据输入转换为16bit数据输出。其中，先到的8bit数据应置于输出16bit的高8位。*/

//34 整数倍数据位宽转换8to16

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

	reg		cnt;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			cnt <= 1'd0;
		else if(valid_in)begin
			if(cnt == 1'd1)
				cnt <= 1'd0;
			else
				cnt <= cnt + 1'b1;
		end
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			valid_out <= 1'b0;
		else if(valid_in & (cnt == 1'd1))
			valid_out <= 1'b1;
		else
			valid_out <= 1'b0;
	end
	
	reg	[7:0]data_lock;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_lock <= 8'd0;
		else if(valid_in)
			data_lock <= data_in;
		else
			data_lock <= data_lock;
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_out <= 12'd0;
      else if(valid_in & cnt == 1'd1)
			data_out <= {data_lock,data_in};
		else
			data_out <= data_out;
	end

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
     reg [7:0]last_in;
     reg cnt;
    
    always @(posedge clk, negedge rst_n) 
        if(!rst_n) 
            cnt <= 1'b0;
        else if(valid_in== 1'b1) 
       //     cnt <= cnt+1'b1;
    //else
            cnt <= ~cnt;
    
    
    always @(posedge clk, negedge rst_n) 
        if(!rst_n) 
            last_in <= 8'd0;
         else if(valid_in) 
            last_in <= data_in;
        else
            last_in <= last_in;
    
    
//    always @(posedge clk, negedge rst_n) 
//        if(!rst_n) 
//            valid_out <= 1'b0;
//    else if(valid_in== 1'b1 && cnt== 1'b1)
//            valid_out <= 1'b1;
//        else
//            valid_out <= 1'b0;
   
    
//    always @(posedge clk, negedge rst_n) 
//        if(!rst_n) 
//            data_out <= 1'b0;
//        else if(valid_in== 1'b1 && cnt== 1'b1)
//            data_out <= {last_in, data_in};
         always @(posedge clk, negedge rst_n) 
             if(!rst_n) begin
            valid_out <= 1'b0;
           data_out <= 1'b0;
             end else if(valid_in== 1'b1 && cnt== 1'b1)
        begin
            valid_out <= 1'b1;
            data_out <= {last_in, data_in};
            end else
            
            valid_out <= 1'b0;
   
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [15:0]   data_out
);

reg [1:0] count ;

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        count<=0;
    else if(valid_in)
	count <=(count == 1)?0:(count + 1);
end


always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        valid_out<=0;
    else if(valid_in&&(count == 1))
		valid_out <=1;
	else
		valid_out <=0;
end


reg [7:0] data_reg;
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        data_reg<=0;
	else
		data_reg <=(valid_in)?data_in:data_reg;
end

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        data_out<=0;
	else if((count == 1)&&valid_in)
		data_out <={data_reg,data_in};
	else 
		data_out <=data_out;
end

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
    reg [7:0] temp;
    reg [1:0] cnt;
    //counter
    always @ (posedge clk or negedge rst_n)
    if(!rst_n)
            cnt <= 0;
    else if(valid_in && cnt != 1)
           cnt <= cnt + 1;
    else if(valid_in && cnt == 1) 
        cnt <= 0;
       //flag
   always @ (posedge clk or negedge rst_n)
    if(!rst_n) 
        valid_out <= 0;
    else if(valid_in && cnt == 1 )
        valid_out <= 1;
    else valid_out <= 0;
    //shift register
   always @ (posedge clk or negedge rst_n)
    if(!rst_n)
        temp <= 0;
    else if(valid_in)
        temp <= data_in;
    
        //output
   always @ (posedge clk or negedge rst_n)
    if(!rst_n)
        data_out <= 0;
    else if(valid_in && cnt == 1)
        data_out <= {temp,data_in};
    
    
        
        
endmodule