Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
    
    
    reg    [3:0]    cnt_bin,gray_reg;
    reg    clk_2;
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) 
            clk_2    <= 1'd0;
        else
            clk_2    <= ~clk_2;        
    end
    
    always@(posedge clk_2 or negedge rst_n) begin
        if(!rst_n) 
            cnt_bin    <= 4'd0;
        else
            cnt_bin    <= cnt_bin + 1'b1;        
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) 
            gray_out    <= 4'd0;
        else
            gray_out    <= cnt_bin ^ (cnt_bin >> 1);        
    end
    
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
    reg [3:0] b;
    reg c; //计时钟
    always @(posedge clk or negedge rst_n) 
        begin
        if(!rst_n) 
            begin 
                b<=0; 
                c<=0;
            end
        else
            begin
                c <= ~c; //c执行010101的周期性变化，用来记两个时钟周期
                b <=(c)? (b+1):b; //c=1时b才加1，两个上升沿记一次
            end      
    end
    
    //根据二进制码到格雷码的转换关系可得
    always @(*) begin
        gray_out[0] <= b[0]^b[1];
        gray_out[1] <= b[1]^b[2];
        gray_out[2] <= b[2]^b[3];
        gray_out[3] <= b[3]^0;
    end


endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);

reg [4:0]cnt;

always@(posedge clk or negedge rst_n)begin
if(!rst_n)
    cnt<=5'd0;
else 
    cnt<=cnt+1'd1;    
end

always@(*)begin
    gray_out=cnt[4:1]^(cnt[4:1]>>1);
end

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
    reg [4:0] bin_cnt;
    wire [3:0] bin;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            bin_cnt <= 5'd0;
        end
        else begin
            bin_cnt <= bin_cnt + 1'b1;
        end
    end
    
    assign bin = bin_cnt[4:1];
    
    //bin2gray
    always @(*) begin
        gray_out = (bin>>1) ^ bin;
    end
    
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
    reg[3:0] binary;
    reg count;
    
    always @ (posedge clk or negedge rst_n)
        if (~rst_n || binary == 15)
            binary <= 0;
        else
            binary <= count ? binary + 1 : binary;
    
    always @ (*)
        gray_out = binary ^ (binary >> 1);
    
    always @ (posedge clk or negedge rst_n)
        if (~rst_n)
            count <= 0;
        else
            count <= ~count;
    
    
    
endmodule