Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module mux(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg data_en_ra,data_en_rb1,data_en_rb2;
reg [3:0]data_in_r;
always@(posedge clk_a or negedge arstn)begin
if(!arstn)begin
data_in_r<=4'd0;
data_en_ra<=1'b0;
end
else begin
data_in_r<=data_in;
data_en_ra<=data_en;
end
end
always@(posedge clk_b or negedge brstn)begin
if(!brstn)begin
data_en_rb1<=1'b0;
data_en_rb2<=1'b0;
end
else begin
data_en_rb1<=data_en_ra;
data_en_rb2<=data_en_rb1;
end
end
always@(posedge clk_b or negedge brstn)begin
if(!brstn)
dataout<=4'd0;
else if(data_en_rb2)
dataout<=data_in_r;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module mux(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg [3:0] data_reg;
reg data_en_a;
reg data_en_b0;
reg data_en_b1;
always @(posedge clk_a or negedge arstn)
begin
if(!arstn)
data_reg <= 0;
else
data_reg <= data_in;
end
always @(posedge clk_a or negedge arstn)
begin
if(!arstn)
data_en_a <= 0;
else
data_en_a <= data_en;
end
always @(posedge clk_b or negedge brstn)
begin
if(!brstn)
begin
data_en_b0 <= 0;
data_en_b1 <= 0;
end
else
data_en_b0 <= data_en_a;
data_en_b1 <= data_en_b0;
end
always @(posedge clk_b or negedge brstn)
begin
if(!brstn)
dataout <=4'b0;
else
dataout <= data_en_b1 ? data_reg : dataout;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module mux(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg [3:0] data_reg;
reg sync_en_d1,sync_en_d2,sync_en_d3;
reg sync_a;
always@(posedge clk_a or negedge arstn) begin
if(!arstn)
data_reg <= 4'd0;
else
data_reg <= data_in;
end
always@(posedge clk_a or negedge arstn) begin
if(!arstn)
sync_a <= 1'd0;
else
sync_a <= data_en;
end
always@(posedge clk_b or negedge brstn) begin
if(!brstn) begin
sync_en_d1 <= 1'd0;
sync_en_d2 <= 1'b0;
sync_en_d3 <= 1'b0;
end
else begin
sync_en_d1 <= sync_a;
sync_en_d2 <= sync_en_d1;
sync_en_d3 <= sync_en_d2;
end
end
always@(posedge clk_b or negedge brstn) begin
if(!brstn)
dataout <= 4'd0;
else if(sync_en_d2)
dataout <= data_reg;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module mux(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg [3:0]data_in1;
reg data_ena,data_enb1,data_enb2;
always@(posedge clk_a or negedge arstn)
if(!arstn)begin
data_in1<=0;
data_ena<=0;
end
else begin
data_in1<=data_in;
data_ena<=data_en;
end
always@(posedge clk_b or negedge brstn)
if(!brstn)begin
data_enb1<=0;
data_enb2<=0;
dataout<=0;
end
else begin
data_enb1<=data_ena;
data_enb2<=data_enb1;
dataout<=(data_enb2==1)?data_in1:dataout;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module mux(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg data_en_a;
always @(posedge clk_a or negedge arstn) begin
if(!arstn) begin
data_en_a <= 1'b0;
end
else begin
data_en_a <= data_en;
end
end
reg [3:0] data_in_a;
always @(posedge clk_a or negedge arstn) begin
if(!arstn) begin
data_in_a <= 4'd0;
end
else begin
data_in_a <= data_in;
end
end
reg data_en_reg;
reg data_en_b;
always @(posedge clk_b or negedge brstn) begin
if(!brstn) begin
data_en_reg <= 1'b0;
data_en_b <= 1'b0;
end
else begin
data_en_reg <= data_en_a;
data_en_b <= data_en_reg;
end
end
always @(posedge clk_b or negedge brstn) begin
if(!brstn) begin
dataout <= 4'd0;
end
else begin
if(data_en_b) begin
dataout <= data_in_a;
end
else begin
dataout <= dataout;
end
end
end
endmodule
