Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);

reg toggle;

always@(posedge clk_fast or negedge rst_n)begin
if(!rst_n)
    toggle<=1'b0;
else if(data_in)
    toggle<=~toggle;
end

reg pulse_syn1,pulse_syn2,dataout_r;

always@(posedge clk_slow or negedge rst_n)begin
if(!rst_n)begin
    pulse_syn1<=1'b0;
    pulse_syn2<=1'b0;
    dataout_r<=1'b0;
end
else begin
    pulse_syn1<=toggle;
    pulse_syn2<=pulse_syn1;
    dataout_r<=pulse_syn2;
end
end

assign dataout=dataout_r^pulse_syn2;

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    
    
    reg    sync,sync_d1,sync_d2,sync_d3;
    
    
    
    always@(posedge clk_fast or negedge rst_n) begin
        if(!rst_n)
            sync    <= 1'b0;            
        else if(data_in)
            sync    <= ~sync;
        else
            sync    <= sync;
    end
    
    always@(posedge clk_slow or negedge rst_n) begin
        if(!rst_n) begin
            sync_d1    <= 1'b0;
            sync_d2    <= 1'b0;
            sync_d3    <= 1'b0;
        end
        else begin
            sync_d1    <= sync;
            sync_d2    <= sync_d1;
            sync_d3    <= sync_d2;
        end
    end
    
    assign dataout = sync_d2 ^ sync_d3;
    
    
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    reg            data_in_reg     ;
    reg            data_in_reg1    ;
    reg            data_in_reg2    ;
    reg            data_in_reg3    ;
    
    assign    dataout= data_in_reg2^data_in_reg3;
    
    
    always@(posedge clk_fast or negedge rst_n )
        begin
            if(rst_n==1'd0)
              data_in_reg <=1'd0;
            else if(data_in==1'd1)
                data_in_reg <= ~ data_in_reg;
            else 
                data_in_reg <=  data_in_reg;
        end   
    
always@(posedge clk_slow or negedge rst_n )
        begin
            if(rst_n==1'd0)
                begin
                   data_in_reg1 <=    1'd0    ;
                   data_in_reg2 <=    1'd0    ;
                   data_in_reg3 <=    1'd0    ;                    
                end
            else 
              begin
                   data_in_reg1 <=    data_in_reg    ;
                   data_in_reg2 <=    data_in_reg1    ;
                   data_in_reg3 <=    data_in_reg2    ;                    
                end
        end 
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    reg data_reg;
    always@(posedge clk_fast or negedge rst_n)
        if(!rst_n)
            data_reg <= 0;
    else 
        data_reg <= (data_in)?   !data_reg : data_reg;
    
    reg data_reg0,data_reg1,data_reg2;
    always@(posedge clk_slow or negedge rst_n)
        if(!rst_n)
            begin
                data_reg0 <= 0;
                data_reg1 <= 0;
                data_reg2 <= 0;
            end
        else
            begin
                data_reg0 <= data_reg;
                data_reg1 <= data_reg0;
                data_reg2 <= data_reg1;
            end
    
    assign dataout = data_reg1 ^ data_reg2;
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    reg data_in_fast;
    always @ (posedge clk_fast or negedge rst_n) begin
        if (~rst_n)
            data_in_fast <= 0;
        else begin
            if (data_in == 1'b1)
                data_in_fast <= ~data_in_fast;
            else
                data_in_fast <= data_in_fast;    
        end
    end
    
    reg data_in_slow_t1;
    reg data_in_slow_t2;
    reg data_in_slow_t3;
    
    always @ (posedge clk_slow or negedge rst_n) begin
        if (~rst_n) begin
            data_in_slow_t1 <= 0;
            data_in_slow_t2 <= 0;
            data_in_slow_t3 <= 0;
        end else begin
            data_in_slow_t1 <= data_in_fast;
            data_in_slow_t2 <= data_in_slow_t1;
            data_in_slow_t3 <= data_in_slow_t2;
        end
        
    end
    
    assign dataout = data_in_slow_t2 ^ data_in_slow_t3;
endmodule