Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);
    
    reg    [7:0]    son[3:0];
    reg    [5:0]    adder_0;
    reg    [5:0]    adder_1;
    
    genvar i;
    generate for(i=0;i<4;i=i+1) begin
        always@(*) begin
            son[i] = mul_b[i] ? mul_a << i : 8'd0;
        end
    end
    endgenerate
    
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) adder_0 <= 'd0;
        else adder_0 <= son[0] + son[1];
    end
     
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) adder_1 <= 'd0;
        else adder_1 <= son[2] + son[3];
    end
     
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) mul_out <= 'd0;
        else mul_out <= adder_0 + adder_1;
    end
    
    
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);
wire [size*2-1:0] mux1;
wire [size*2-1:0] mux2;
wire [size*2-1:0] mux3;
wire [size*2-1:0] mux4;
reg [size*2-1:0] mux12;
reg [size*2-1:0] mux34;
assign mux1=(mul_b[0]==1)?{4'd0,mul_a}:8'd0;
assign mux2=(mul_b[1]==1)?{3'd0,mul_a,1'b0}:8'd0;
assign mux3=(mul_b[2]==1)?{2'd0,mul_a,2'd0}:8'd0;
assign mux4=(mul_b[3]==1)?{1'd0,mul_a,3'd0}:8'd0;

    always@(posedge clk or negedge rst_n)
      if(rst_n==0)
        begin
   mux12<=0;
   mux34<=0;
        end
     else
         begin
     mux12<=mux1+mux2;
   mux34<=mux3+mux4;           
         end
    
always@(posedge clk or negedge rst_n)
    if(rst_n==0)
        begin
      mul_out<=0;

        end
    
    else 
        begin

      mul_out<=mux12+mux34;

        end

endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);
    reg [size*2-1:0] mul_tmp [size-1:0];
    integer i;
    integer j;
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            for(i=0; i<size; i=i+1) begin
                mul_tmp[i] = 'b0;
            end
        end
        else begin
            for(j=0; j<size; j=j+1) begin
                mul_tmp[j] = mul_b[j]? (mul_a<<j): 'b0;
            end
        end
    end
    
    reg [size*2-1:0] sum_tmp [size-1:0];
    integer n;
    always @(*) begin
        for(n=0; n<size; n=n+1) begin
            if(n==0) begin
                sum_tmp[0] = mul_tmp[0];
            end
            else begin
                sum_tmp[n] = sum_tmp[n-1] + mul_tmp[n];
            end
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            mul_out <= 'b0;
        end
        else begin
            mul_out <= sum_tmp[size-1];
        end
    end
        
        
        
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);
    
    reg [7:0] addr01;
    reg [7:0] addr02;
    
    wire [7:0] temp0;
    wire [7:0] temp1;
    wire [7:0] temp2;
    wire [7:0] temp3;
    
    assign temp0=(mul_b[0])?{4'd0,mul_a}:8'd0;
    assign temp1=(mul_b[1])?{3'd0,mul_a,1'd0}:8'd0;
    assign temp2=(mul_b[2])?{2'd0,mul_a,2'd0}:8'd0;
    assign temp3=(mul_b[3])?{1'd0,mul_a,3'd0}:8'd0;
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
           addr01<=0;
            addr02<=0;
        end
        else begin
            addr01<=temp0+temp1;
            addr02<=temp2+temp3;
        end    
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            mul_out<=0;
        else 
            mul_out<=addr01+addr02;
    end
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);
    wire [size*2:0]mul_1, mul_2, mul_3, mul_4;
  wire [size*2-1:0]sum_1, sum_2, sum_3;
  reg  [size*2:0]mul_r1, mul_r2, mul_r3, mul_r4;
  reg  [size*2-1:0]sum_r1, sum_r2, sum_r3;
   
  assign mul_1 = mul_b[0]? mul_a: 0;
  assign mul_2 = mul_b[1]? mul_a<<1: 0;
  assign mul_3 = mul_b[2]? mul_a<<2: 0;
  assign mul_4 = mul_b[3]? mul_a<<3: 0;
   
  always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
      mul_r1 <= 0;
    else
      mul_r1 <= mul_1;
  end
  always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
      mul_r2 <= 0;
    else
      mul_r2 <= mul_2;
  end
  always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
      mul_r3 <= 0;
    else
      mul_r3 <= mul_3;
  end
  always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
      mul_r4 <= 0;
    else
      mul_r4 <= mul_4;
  end
   
  assign sum_1 = {size*(1'b0),mul_r1} + {size*(1'b0),mul_r2};
  assign sum_2 = {size*(1'b0),mul_r3} + {size*(1'b0),mul_r4};
   
  always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
      sum_r1 <= 0;
    else
      sum_r1 <= sum_1;
  end
   
  always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
      mul_out <= 0;
    else
      mul_out <= sum_1 + sum_2;
  end
         
endmodule