VL15. 优先编码器Ⅰ
描述
①请根据该功能表，用Verilog实现该优先编码器Ⅰ。
|
EI |
I[7] |
I[6] |
I[5] |
I[4] |
I[3] |
I[2] |
I[1] |
I[0] |
Y[2] |
Y[1] |
Y[0] |
GS |
EO |
|
0 |
x |
x |
x |
x |
x |
x |
x |
x |
0 |
0 |
0 |
0 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
|
1 |
1 |
x |
x |
x |
x |
x |
x |
x |
1 |
1 |
1 |
1 |
0 |
|
1 |
0 |
1 |
x |
x |
x |
x |
x |
x |
1 |
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
1 |
x |
x |
x |
x |
x |
1 |
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
1 |
x |
x |
x |
x |
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
1 |
x |
x |
x |
0 |
1 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
1 |
x |
x |
0 |
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
x |
0 |
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
输入描述
input [7:0] I ,输出描述
output wire [2:0] Y ,Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
reg[2:0] YY;
reg GSS;
reg EOO;
always@(*)
begin
if(~EI)
begin
YY=0;
GSS=0;
EOO=0;
end
if(EI)
begin
casex(I)
8'b0000_0000: begin YY=0; GSS=0; EOO=1; end
8'b1xxx_xxxx: begin YY=3'd7; GSS=1; EOO=0; end
8'b01xx_xxxx: begin YY=3'd6; GSS=1; EOO=0; end
8'b001x_xxxx: begin YY=3'd5; GSS=1; EOO=0; end
8'b0001_xxxx: begin YY=3'd4; GSS=1; EOO=0; end
8'b0000_1xxx: begin YY=3'd3; GSS=1; EOO=0; end
8'b0000_01xx: begin YY=3'd2; GSS=1; EOO=0; end
8'b0000_001x: begin YY=3'd1; GSS=1; EOO=0; end
8'b0000_0001: begin YY=0; GSS=1; EOO=0; end
endcase
end
end
assign Y=YY;
assign GS=GSS;
assign EO=EOO;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
reg [2:0]Y_tmp;
assign EO=EI&(!(|I));
always@(*)
casex(I)
8'b00000000:Y_tmp=3'd0;
8'b00000001:Y_tmp=3'd0;
8'b0000001x:Y_tmp=3'd1;
8'b000001xx:Y_tmp=3'd2;
8'b00001xxx:Y_tmp=3'd3;
8'b0001xxxx:Y_tmp=3'd4;
8'b001xxxxx:Y_tmp=3'd5;
8'b01xxxxxx:Y_tmp=3'd6;
8'b1xxxxxxx:Y_tmp=3'd7;
default:Y_tmp=3'd0;
endcase
assign Y=EI?Y_tmp:3'd0;
assign GS=~((~EI)|(EI&(~(|I))));
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
reg [2:0] Y_tmp;
always@(*) begin
if(~EI) begin
Y_tmp = 3'b000;
end
else begin
casex (I)
8'b00000000 : Y_tmp = 3'b000;
8'b1xxxxxxx : Y_tmp = 3'b111;
8'b01xxxxxx : Y_tmp = 3'b110;
8'b001xxxxx : Y_tmp = 3'b101;
8'b0001xxxx : Y_tmp = 3'b100;
8'b00001xxx : Y_tmp = 3'b011;
8'b000001xx : Y_tmp = 3'b010;
8'b0000001x : Y_tmp = 3'b001;
8'b00000001 : Y_tmp = 3'b000;
default: Y_tmp = 3'b000;
endcase
end
end
assign Y = Y_tmp;
assign GS = EI&(| I);
assign EO = EI&(~GS);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output reg [2:0] Y ,
output wire GS ,
output wire EO
);
always@(*)
begin
casex({EI, I})
9'b0_xxxx_xxxx: Y = 3'd0;
9'b1_0000_0000: Y = 3'd0;
9'b1_1xxx_xxxx: Y = 3'd7;
9'b1_01xx_xxxx: Y = 3'd6;
9'b1_001x_xxxx: Y = 3'd5;
9'b1_0001_xxxx: Y = 3'd4;
9'b1_0000_1xxx: Y = 3'd3;
9'b1_0000_01xx: Y = 3'd2;
9'b1_0000_001x: Y = 3'd1;
9'b1_0000_0001: Y = 3'd0;
default: ;
endcase
end
assign GS = EI & (|I);
assign EO = (~(|I)) & EI;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
reg [2:0] Yi ;
assign EO = I==0 && EI;
assign GS = ~(I==0) && EI;
always @(*)
casez(I)
8'b1???_???? : assign Yi = 3'b111;
8'b01??_???? : assign Yi = 3'b110;
8'b001?_???? : assign Yi = 3'b101;
8'b0001_???? : assign Yi = 3'b100;
8'b0000_1??? : assign Yi = 3'b011;
8'b0000_01?? : assign Yi = 3'b010;
8'b0000_001? : assign Yi = 3'b001;
default : assign Yi = 3'b000;
endcase
assign Y = (EI ==0 )? 0 :Yi;
endmodule