VL16. 使用8线-3线优先编码器Ⅰ实现16线-4线优先编码器
描述
module encoder_83( input [7:0] I , input EI , output wire [2:0] Y , output wire GS , output wire EO ); assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]); assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]); assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]); assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0]; assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]); //assign GS = EI&(| I); endmodule
|
EI |
I[7] |
I[6] |
I[5] |
I[4] |
I[3] |
I[2] |
I[1] |
I[0] |
Y[2] |
Y[1] |
Y[0] |
GS |
EO |
|
0 |
x |
x |
x |
x |
x |
x |
x |
x |
0 |
0 |
0 |
0 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
|
1 |
1 |
x |
x |
x |
x |
x |
x |
x |
1 |
1 |
1 |
1 |
0 |
|
1 |
0 |
1 |
x |
x |
x |
x |
x |
x |
1 |
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
1 |
x |
x |
x |
x |
x |
1 |
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
1 |
x |
x |
x |
x |
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
1 |
x |
x |
x |
0 |
1 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
1 |
x |
x |
0 |
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
x |
0 |
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
输入描述
input [15:0] A ,输出描述
output wire [3:0] L ,Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
endmodule
module encoder_164(
input [15:0] A ,
input EI ,
output wire [3:0] L ,
output wire GS ,
output wire EO
);
wire EO_1,EO_2;
wire GS_1,GS_2;
wire [2:0]Y_1;
wire [2:0]Y_2;
encoder_83 encoder_1(A[7:0],EI,Y_1,GS_1,EO_1);
encoder_83 encoder_2(A[15:8],EI,Y_2,GS_2,EO_2);
assign L=(EI&(|A[15:8]))?{1'b1,Y_2}:{1'b0,Y_1};
assign GS=~((~GS_1)&(~GS_2));
assign EO=EO_1&EO_2;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
endmodule
module encoder_164(
input [15:0] A ,
input EI ,
output wire [3:0] L ,
output wire GS ,
output wire EO
);
wire EO1;
wire GS1, GS2;
wire[2:0] LL, LH;
assign GS = GS1 | GS2;
assign L[3] = GS2;
assign L[2:0] = (GS2)? LH : LL;
encoder_83 encoder_83_M0(
.I(A[7:0]) ,
.EI(EO1) ,
.Y(LL) ,
.GS(GS1) ,
.EO(EO)
);
encoder_83 encoder_83_M1(
.I(A[15:8]) ,
.EI(EI) ,
.Y(LH) ,
.GS(GS2) ,
.EO(EO1)
);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
endmodule
module encoder_164(
input [15:0] A ,
input EI ,
output wire [3:0] L ,
output wire GS ,
output wire EO
);
wire EI_0;
wire GS_0;
wire GS_1;
wire [2:0] y0;
wire [2:0] y1;
encoder_83 encoder_83_r1(
.I (A[15:8]),
.EI (EI),
.Y (y0),
.GS (GS_0),
.EO (EI_0)
);
encoder_83 encoder_83_r2(
.I (A[7:0]),
.EI (EI_0),
.Y (y1),
.GS (GS_1),
.EO (EO)
);
assign L[3] = GS_0;
assign L[2] = y1[2] | y0[2];
assign L[1] = y1[1] | y0[1];
assign L[0] = y1[0] | y0[0];
assign GS = GS_1 | GS_0;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
endmodule
module encoder_164(
input [15:0] A ,
input EI ,
output wire [3:0] L ,
output wire GS ,
output wire EO
);
wire E0;
wire gs1;
wire gs2;
wire [3:0]L1;
wire [3:0]L2;
encoder_83 code(.I(A[15:8]), .EI(EI), .Y(L1[2:0]), .GS(gs1), .EO(E0));
encoder_83 cood(.I(A[7:0]), .EI(E0), .Y(L2[2:0]), .GS(gs2), .EO(EO));
assign L[3] = gs1;
assign GS = gs1 | gs2;
assign L[0] = L1[0] | L2[0];
assign L[1] = L1[1] | L2[1];
assign L[2] = L1[2] | L2[2];
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05
`timescale 1ns/1ns
module encoder_83(
input [7:0] I ,
input EI ,
output wire [2:0] Y ,
output wire GS ,
output wire EO
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
endmodule
module encoder_164(
input [15:0] A ,
input EI ,
output wire [3:0] L ,
output wire GS ,
output wire EO
);
wire [2:0] Y1,Y2,L1;
wire GS1,EO1,GS2;
encoder_83 u0(
.I(A[15:8]),
.EI(EI),
.Y(Y1),
.GS(GS1),
.EO(EO1)
);
encoder_83 u1(
.I(A[7:0]),
.EI(EO1),
.Y(Y2),
.GS(GS2),
.EO(EO)
);
assign L1=Y1|Y2;
assign L={GS1,L1};
assign GS=GS1|GS2;
endmodule