VL12. 4bit超前进位加法器电路
描述
4bit超前进位加法器的逻辑表达式如下：
中间变量
和：，进位：
请用Verilog语言采用门级描述方式，实现此4bit超前进位加法器，接口电路如下：
输入描述
输入信号：
A_in[3:0],
B_in[3:0]
C_1
类型：wire
输出描述
输出信号：
S[3:0]
CO
类型：wire
VL12. 4bit超前进位加法器电路
描述
4bit超前进位加法器的逻辑表达式如下：
中间变量
和：，进位：
输入描述
输出描述
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module lca_4(
input [3:0] A_in ,
input [3:0] B_in ,
input C_1 ,
output wire CO ,
output wire [3:0] S
);
and G0(G0_o, A_in[0], B_in[0]),
G1(G1_o, A_in[1], B_in[1]),
G2(G2_o, A_in[2], B_in[2]),
G3(G3_o, A_in[3], B_in[3]),
ad0(ad0_o, P0_o, C_1),
ad1(ad1_o, P1_o, G0_o),
ad2(ad2_o, P1_o, P0_o, C_1),
ad3(ad3_o, P2_o, G1_o),
ad4(ad4_o, P2_o, P1_o, G0_o),
ad5(ad5_o, P2_o, P1_o, P0_o, C_1),
ad6(ad6_o, P3_o, G2_o),
ad7(ad7_o, P3_o, P2_o, G1_o),
ad8(ad8_o, P3_o, P2_o, P1_o, G0_o),
ad9(ad9_o, P3_o, P2_o, P1_o, P0_o, C_1);
or C0(C0_o, G0_o, ad0_o),
C1(C1_o, G1_o, ad1_o, ad2_o),
C2(C2_o, G2_o, ad3_o, ad4_o, ad5_o),
C3(CO, G3_o, ad6_o, ad7_o, ad8_o, ad9_o);
xor P0(P0_o, A_in[0], B_in[0]),
P1(P1_o, A_in[1], B_in[1]),
P2(P2_o, A_in[2], B_in[2]),
P3(P3_o, A_in[3], B_in[3]);
xor nr0(S[0], P0_o, C_1),
nr1(S[1], P1_o, C0_o),
nr2(S[2], P2_o, C1_o),
nr3(S[3], P3_o, C2_o);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module lca_4(
input [3:0] A_in ,
input [3:0] B_in ,
input C_1 ,
output wire CO ,
output wire [3:0] S
);
wire [3:0] C;
full_add u_add0(
.a (A_in[0]),
.b (B_in[0]),
.c (C_1 ),
.s (S[0] ),
.co (C[0] )
);
full_add u_add1(
.a (A_in[1]),
.b (B_in[1]),
.c (C[0] ),
.s (S[1] ),
.co (C[1] )
);
full_add u_add2(
.a (A_in[2]),
.b (B_in[2]),
.c (C[1] ),
.s (S[2] ),
.co (C[2] )
);
full_add u_add3(
.a (A_in[3]),
.b (B_in[3]),
.c (C[2] ),
.s (S[3] ),
.co (C[3] )
);
assign CO = C[3];
endmodule
module full_add (
input a,
input b,
input c,
output s,
output co
);
assign s = (a & b & c) | (~a & ~b & c) | (~a & b & ~c) | (a & ~b & ~c);
assign co = (a & b) | (a & c) | (b &c);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module lca_4(
input [3:0] A_in ,
input [3:0] B_in ,
input C_1 ,
output wire CO ,
output wire [3:0] S
);
wire [3:0]G;
wire[3:0]P;
assign G[0] = A_in[0] & B_in[0];
assign G[1] = A_in[1] & B_in[1];
assign G[2] = A_in[2] & B_in[2];
assign G[3] = A_in[3] & B_in[3];
assign P[0] = A_in[0] ^ B_in[0];
assign P[1] = A_in[1] ^ B_in[1];
assign P[2] = A_in[2] ^ B_in[2];
assign P[3] = A_in[3] ^ B_in[3];
wire [3:0] C;
assign S[0] = P[0] ^ C_1;
assign S[1] = P[1] ^ C[0];
assign S[2] = P[2] ^ C[1];
assign S[3] = P[3] ^ C[2];
assign CO = C[3];
assign C[0] = G[0] | P[0]&C_1;
assign C[1] = G[1] | P[1]&C[0];
assign C[2] = G[2] | P[2]&C[1];
assign C[3] = G[3] | P[3]&C[2];
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module lca_4(
input [3:0] A_in ,
input [3:0] B_in ,
input C_1 ,
output wire CO ,
output wire [3:0] S
);
wire[3:0] C;
full_add full_add_U0(
.a(A_in[0]),
.b(B_in[0]),
.c(C_1),
.s(S[0]),
.co(C[0])
);
full_add full_add_U1(
.a(A_in[1]),
.b(B_in[1]),
.c(C[0]),
.s(S[1]),
.co(C[1])
);
full_add full_add_U2(
.a(A_in[2]),
.b(B_in[2]),
.c(C[1]),
.s(S[2]),
.co(C[2])
);
full_add full_add_U3(
.a(A_in[3]),
.b(B_in[3]),
.c(C[2]),
.s(S[3]),
.co(C[3])
);
assign CO=C[3];
endmodule
module full_add(
input a,
input b,
input c,
output s,
output co
);
assign s=(a^b)^c;
assign co=(a & b) | (a & c) | (b &c);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module lca_4(
input [3:0] A_in ,
input [3:0] B_in ,
input C_1 ,
output wire CO ,
output wire [3:0] S
);
wire [3:0] G;
wire [3:0] P;
assign G=A_in&B_in;
assign P=A_in^B_in;
wire [3:0]C;
assign C[0]=G[0]|(P[0]&C_1);
assign C[1]=G[1]|(P[1]&C[0]);
assign C[2]=G[2]|(P[2]&C[1]);
assign C[3]=G[3]|(P[3]&C[2]);
assign S[0]=P[0]^C_1;
assign S[1]=P[1]^C[0];
assign S[2]=P[2]^C[1];
assign S[3]=P[3]^C[2];
assign CO=C[3];
endmodule