Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
    
    wire [7:0]res1,res2;
    reg [8:0]c_r,c_r2;
    
    mult mult_u1(
        .a(a),
        .b(12),
        .res(res1)
);
    
     mult mult_u2(
         .a(b),
         .b(5),
         .res(res2)
);
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            c_r <= 'd0;
        else
            c_r <= res1 + res2;
    end 
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            c_r2 <= 'd0;
        else
            c_r2 <= c_r;
    end
    
    assign c = c_r2;
    
endmodule

module mult(
    a,
    b,
    res
);
    input [3:0]a;
    input [3:0]b;
    output [7:0]res;
    
    wire [7:0]a_shift[3:0];
    
    
    genvar i;
    generate
        for(i=0;i<4;i=i+1) begin:cycle
            assign a_shift[i] = b[i]? {a,{(i){1'b0}}} :'d0;
        end 
    endgenerate
    
    assign res = a_shift[0] + a_shift[1] + a_shift[2] + a_shift[3];

    
endmodule 

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
    
    reg [8:0] a_next,b_next,c_next;
    always @(posedge clk )
        if(!rst_n) begin
            a_next <= 'b0;
            b_next <= 'b0;
            c_next <= 'b0;
        end
        else begin
            a_next <= (a<<2) + (a<<3);
            b_next <= (b<<2) + b;
            c_next <= a_next + b_next;
        end
            

    assign c = c_next;
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
    
    reg [7:0] a_temp;
    reg [7:0] b_temp;
    reg [7:0] c_temp;
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 0)begin
            a_temp <= 0;
        end
        else begin
            a_temp <= (a <<3) + (a<<2);
        end
    end
     always@(posedge clk or negedge rst_n)begin
        if(rst_n == 0)begin
            b_temp <= 0;
        end
        else begin
            b_temp <= (b <<2) + (b);
        end
    end   
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 0)begin
            c_temp <= 0;
        end
        else begin
            c_temp <= a_temp + b_temp;
        end
    end
    assign c = c_temp ;
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
    reg [8:0]temp1,temp2;
    reg [8:0]add;
    always @(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
            temp1 <= 'b0;
            temp2 <= 'b0;
            add <= 'b0;
        end
        else begin
            temp2 <= (b << 3)-(b<<1)-b;
            temp1 <= (a<<4)-(a<<1)-a-a;
            add <= temp1 + temp2;
        end
    end
    assign c = add;
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-05

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output reg [8:0] c
	);
    
    wire [8:0] c1,c2;
    mul mul_1(
        .a(a),
        .b('d12),
        .c(c1)
    );
    mul mul_2(
        .a(b),
        .b('d5),
        .c(c2)
    );
    reg [8:0] c_r;
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            c_r <= 9'd0;
        else
            c_r <= c1 + c2;
     always@(posedge clk or negedge rst_n)
        if(!rst_n)
            c <= 9'd0;
        else
            c <= c_r;   
    
endmodule

module mul(
    input [3:0] a,
    input [3:0] b,
    output [7:0] c
    );
        
    wire [7:0]mid_1,mid_2,mid_3,mid_4;
    
    assign mid_1=(b[0])?a:'b0;
    assign mid_2=(b[1])?{a,1'b0}:'b0;
    assign mid_3=(b[2])?{a,2'b0}:'b0;
    assign mid_4=(b[3])?{a,3'b0}:'b0;
    
    assign c= mid_1+ mid_2 +mid_3 +mid_4;
    
endmodule