Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
    reg [2:0]cnt1;
    reg [2:0]cnt2;
    reg div1;
    reg div2;
    
    always@(posedge clk_in or negedge rst)
        begin
            if(~rst)
                cnt1 <= 3'h0;
            else
                begin
                    if(cnt1==3'h4)
                    cnt1 <= 3'h0;
                else
                    cnt1 <= cnt1 + 3'h1;
                end
        end
    
    
    always@(posedge clk_in or negedge rst)
        begin
            if(~rst)
                div1 <= 1'b0;
            else
                begin
                    if((cnt1==3'h0)|(cnt1==3'h2))
                    div1 <= ~div1;
                else
                    div1 <= div1;
                end
        end
    
assign clk_out5 = div1 ;

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
    reg [2:0] cnt;
    reg reg_clk;
    always@(posedge clk_in or negedge rst)begin
        if(!rst)
            cnt <= 0;
        else 
            cnt <= cnt == 4 ? 0 : cnt + 1;
    end
    always@(posedge clk_in or negedge rst)begin
        if(!rst)
            reg_clk <= 0;
        else 
            reg_clk <= cnt<= 1;
    end
    assign clk_out5 = reg_clk;
    

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
    
    parameter    N = 5;
    reg    [3:0]    cnt;
    reg             clk_out5_r;
    
    always @(posedge clk_in or negedge rst) begin
        if (rst == 0) begin
            cnt <= 'd0;
        end
        else begin
            cnt <= (cnt == (N-1)) ? 'd0 : (cnt+1);
        end
    end
    
    always @(posedge clk_in or negedge rst) begin
        if (rst == 0) begin
            clk_out5_r <= 1'b0;
        end
        else if (cnt == 0) begin
            clk_out5_r <= ~clk_out5_r;
        end
        else if (cnt == (N-1)/2) begin
            clk_out5_r <= ~clk_out5_r;
        end
    end
    
    assign clk_out5 = clk_out5_r;


//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output     clk_out5
);
//*************code***********//

    parameter N=5; //鍒嗛鍙傛暟
    reg [2:0]cnt;


always@(posedge clk_in or negedge rst)
    if(!rst)
        cnt <= 3'd0;
    else if(cnt == N-1)
    cnt <= 3'd0;
else
    cnt <= cnt + 1'b1;
 
 
assign    clk_out5 = ((cnt > 3'd0)&&(cnt <= 3'd2))? 1'b1:1'b0;


//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
    reg [2:0] cnt;
    always @ (posedge clk_in or negedge rst) begin
        if(~rst) begin
            cnt <= 3'b0;
        end
        else begin
            if(cnt == 3'd4) begin
                cnt <= 3'd0;
            end 
            else begin
                cnt <= cnt + 3'd1;
            end 
        end 
    end 

    reg clk_out5_r;
    always @ (posedge clk_in or negedge rst) begin
        if(~rst) begin
            clk_out5_r <= 3'b0;
        end
        else begin
            case( cnt ) 
                3'd0 : clk_out5_r <= 1'b1;
                3'd1 : clk_out5_r <= 1'b1;
                3'd2 : clk_out5_r <= 1'b0;
                3'd3 : clk_out5_r <= 1'b0;
                3'd4 : clk_out5_r <= 1'b0;
                default : clk_out5_r <= 1'b0;
            endcase
        end 
    end 

    assign clk_out5 = clk_out5_r;
    
//*************code***********//
endmodule