Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg q1;
    always @(posedge clk or negedge rst)
        if (~rst) begin
                q1 <=    1'b0;
                q  <=    1'b0;
            end
            else begin
                if(data) begin
                    q1 <=    !q1;    
                end
                if(q1) begin
                        q <= !q;
                end
            end
//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg q1;
    always @(posedge clk or negedge rst)
        if(!rst)
            q1 <= 1'b0;
        else if(data)
            q1 <= ~q1;
        else
            q1 <= q1;
    
    always @(posedge clk or negedge rst)
        if(!rst)
            q <= 1'b0;
        else if(q1)
            q <= ~q;
        else
            q <= q;
    
            

//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg data_1 = 1'b0;
    always @(posedge clk or negedge rst) begin
        if(!rst) 
            data_1 <= 1'b0;
        else 
            data_1 <= data ^ data_1;
    end
    
    always @(posedge clk or negedge rst) begin
        if(!rst) 
            q <= 1'b0;
        else 
            q <= data_1 ^ q;
    end


            
//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg data1 ;
    always@(posedge clk or negedge rst)
        begin
            if(rst == 1'b0)
                data1 <= 1'b0;
            else
                data1 <= data^data1;
        end
    always@(posedge clk or negedge rst)
        begin
            if(rst == 1'b0)
                q <= 1'b0;
            else
                q <= q^data1;
        end
//*************code***********//
endmodule

Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg data_1;
   always @ (posedge clk or negedge rst) begin
       if (!rst)
           data_1 <= 1'b0;
       else
           data_1 <= data ^ data_1 ;
   end
     
   always @ (posedge clk or negedge rst) begin
       if (!rst)
           q <= 1'b0;
       else
           q <= data_1 ^ q;
   end

//*************code***********//
endmodule