VL30. 数据串转并电路
描述
实现串并转换电路，输入端输入单bit数据，每当本模块接收到6个输入数据后，输出端输出拼接后的6bit数据。本模块输入端与上游的采用valid-ready双向握手机制，输出端与下游采用valid-only握手机制。数据拼接时先接收到的数据放到data_b的低位。
输入描述
input clk ,输出描述
output reg ready_a ,Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [5:0] data_b_reg;
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
cnt<='d0;
else if(valid_a&&ready_a)
cnt<=(cnt=='d5)?'d0:cnt+1;
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
ready_a<='d0;
else
ready_a<='d1;
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
valid_b<='d0;
else if(cnt=='d5)
valid_b<='d1;
else if(valid_b=='d1)
valid_b<='d0;
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
data_b_reg<='d0;
else if(valid_a&&ready_a)
data_b_reg<={data_a,data_b_reg[5:1]};
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)
data_b<='d0;
else if(cnt=='d5)
data_b<={data_a,data_b_reg[5:1]};
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg unsigned[2:0] cnt;
reg [5:0] temp;
always@(posedge clk,negedge rst_n)begin
if(~rst_n)
cnt <= 0;
else if((cnt<5) &valid_a)
cnt <= cnt + 1;
else if((cnt<5) &(~valid_a))
cnt <= cnt;
else
cnt <= 0;
end
always@(posedge clk,negedge rst_n)begin
if(~rst_n)begin
temp <= 0;
end
else if(valid_a)begin
temp <= {data_a,temp[5:1]};
end
else begin
temp <= temp;
end
end
always@(posedge clk,negedge rst_n)begin
if(~rst_n)
data_b <= 0;
else if(cnt==5)
data_b <= {data_a,temp[5:1]};
else
data_b <= data_b;
end
//assign ready_a = 1'b1;
//assign valid_b = (cnt==6) ? 1:0;
always@(posedge clk,negedge rst_n)begin
if(~rst_n)
ready_a <= 1'b0;
else
ready_a <= 1'b1;
end
always@(posedge clk,negedge rst_n)begin
if(~rst_n)
valid_b <= 0;
else if(cnt==5)
valid_b <= 1'b1;
else
valid_b <= 0;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [5:0] shift_r;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
shift_r <= 6'd0;
else if(valid_a)
shift_r <= {data_a, shift_r[5:1]};
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
data_b <= 6'd0;
else if(cnt == 3'd5 && valid_a)
data_b <= {data_a, shift_r[5:1]};
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
ready_a <= 1'b0;
else
ready_a <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
cnt <= 3'd0;
else if(cnt == 3'd5 && valid_a)
cnt <= 3'd0;
else if(valid_a)
cnt <= cnt + 1'd1;
else
cnt <= cnt;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
valid_b <= 1'd0;
else if(cnt == 3'd5)
valid_b <= 1'd1;
else
valid_b <= 1'd0;
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [5:0] r_shift;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ready_a <= 0;
end
else begin
ready_a <= 1;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
r_shift <= 0;
cnt <= 0;
end
else if(valid_a) begin
r_shift <= {data_a,r_shift[5:1]};
cnt <= (cnt == 3'b101) ? 0 : cnt + 1;
end
else begin
r_shift <= r_shift;
cnt <= cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
valid_b <= 0;
data_b <= 0;
end
else if(cnt == 3'b101) begin
valid_b <= 1;
data_b <= {data_a,r_shift[5:1]};
end
else begin
valid_b <= 0;
data_b <= data_b;
end
end
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [5:0] data_r;
//ready_a 就一直是1 ，
//cnt 捂手前提下，若为5 则下一个 0，循环六个计数
// reg 暂存的 一旦捂手就存一个。
//valid_b 当==5的时候，且 捂手了，则有效一个t
//data_b 当==5的时候，且捂手了，现场塞一个，输出，
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ready_a <= 1'b0;
end else begin
ready_a <= 1'b1;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 3'b0;
data_r <= 6'b0;
end else if (ready_a& valid_a)begin
cnt <= (cnt== 'd5)?'d0:cnt+1'b1;
data_r <= {data_a,data_r[5:1]};
end else begin
cnt <= cnt;
data_r <= data_r;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
valid_b <= 1'b0;
data_b <= 6'b0;
end else if ((ready_a& valid_a)&(cnt=='d5))begin
valid_b <= 1'b1;
data_b <= {data_a,data_r[5:1]};
end else begin
valid_b <= 1'b0;
data_b <= data_b;
end
end
endmodule