VL22. 根据状态转移图实现时序电路
描述
某同步时序电路的状态转换图如下，→上表示“C/Y”，圆圈内为现态，→指向次态。
请使用D触发器和必要的逻辑门实现此同步时序电路，用Verilog语言描述。
电路的接口如下图所示，C是单bit数据输入端。
输入描述
input C ,input clk ,
input rst_n
输出描述
output wire YVL22. 根据状态转移图实现时序电路
描述
某同步时序电路的状态转换图如下，→上表示“C/Y”，圆圈内为现态，→指向次态。
输入描述
input C ,输出描述
output wire YVerilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seq_circuit(
input C ,
input clk ,
input rst_n,
output wire Y
);
////-----------------------
//// STATE MACHINE
////-----------------------
reg [1:0] state, next_state;
parameter S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b11,
S3 = 2'b10;
// state transfer
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
state <= S0;
else
state <= next_state;
end
// logic for next state
always @(*) begin
next_state = S0;
case(state)
S0:
if(C==1'b1)
next_state = S1;
else
next_state = S0;
S1:
if(C==1'b0)
next_state = S2;
else
next_state = S1;
S2:
if(C==1'b1)
next_state = S3;
else
next_state = S2;
S3:
if(C==1'b0)
next_state = S0;
else
next_state = S3;
default:
next_state = state;
endcase
end
assign Y = (state==S3 & C==1'b1) | (state==S2);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seq_circuit(
input C ,
input clk ,
input rst_n,
output wire Y
);
reg [1:0]crnt_state;
reg [1:0]next_state;
reg y;
always @ (posedge clk or negedge rst_n) begin
if (~rst_n) begin
crnt_state <= 2'b00;
next_state <= 2'b00;
end
else
crnt_state <= next_state;
end
always @ (*) begin
case (crnt_state)
2'b00: begin
if (C == 0)
next_state = 2'b00;
else
next_state = 2'b01;
end
2'b01: begin
if (C == 0)
next_state = 2'b11;
else
next_state = 2'b01;
end
2'b10: begin
if (C == 0)
next_state = 2'b00;
else
next_state = 2'b10;
end
2'b11: begin
if (C == 0)
next_state = 2'b11;
else
next_state = 2'b10;
end
endcase
end
always @ (*) begin
if (~rst_n)
y <= 1'b0;
else if ((crnt_state == 2'b11) | ((crnt_state == 2'b10) & (C == 1)))
y <= 1'b1;
else
y <= 1'b0;
end
assign Y = y;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seq_circuit(
input C ,
input clk ,
input rst_n,
output wire Y
);
reg [1:0] state, next_state;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state <= 0;
next_state<=0; end
else
state <= next_state;
end
always @(*) begin
next_state = 2'b00;
case(state)
2'b00: next_state = C? 2'b01: 2'b00;
2'b01: next_state = C? 2'b01: 2'b11;
2'b10: next_state = C? 2'b10: 2'b00;
2'b11: next_state = C? 2'b10: 2'b11;
default: next_state = state;
endcase
end
assign Y = (next_state == 2'b10) | (state == 2'b11);
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seq_circuit(
input C ,
input clk ,
input rst_n,
output wire Y
);
// reg [1:0] state;
reg [1:0] cur_state;
reg [1:0] nex_state;
reg y;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cur_state<=0;
else
cur_state<=nex_state;
end
always@(*)
case (cur_state)
2'b00:
if(C==0)begin
nex_state=2'b00;
y=0;
end
else begin
nex_state=2'b01;
y=0;
end
2'b01:
if(C==0)begin
nex_state=2'b11;
y=0;
end
else begin
nex_state=2'b01;
y=0;
end
2'b10:
if(C==0)begin
nex_state=2'b00;
y=0;
end
else begin
nex_state=2'b10;
y=1;
end
2'b11:
if(C==0)begin
nex_state=2'b11;
y=1;
end
else begin
nex_state=2'b10;
y=1;
end
default;
endcase
assign Y=y;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module seq_circuit(
input C ,
input clk ,
input rst_n,
output wire Y
);
localparam x00=2'b00,
x01=2'b01,
x11=2'b11,
x10=2'b10;
reg Y1;
reg [1:0] state_c;
reg [1:0] state_n;
always@(posedge clk,negedge rst_n)begin
if(!rst_n)
state_c<=x00;
else
state_c<=state_n;
end
always@(*)begin
case(state_c)
x00:begin
if(C==0)
state_n<=state_c;
else
state_n<=x01;
end
x01:begin
if(C==0)
state_n<=x11;
else
state_n<=state_c;
end
x11:begin
if(C==0)
state_n<=state_c;
else
state_n<=x10;
end
x10:begin
if(C==0)
state_n<=x00;
else
state_n<=state_c;
end
default:state_n<=state_c;
endcase
end
always@(*)begin
if(state_c==x11||(state_c==x10&&C==1))
Y1=1'b1;
else
Y1=1'b0;
end
assign Y=Y1;
endmodule