VL18. 实现3-8译码器①
描述
下表是74HC138译码器的功能表.
|
E3 |
E2_n |
E1_n |
A2 |
A1 |
A0 |
Y0_n |
Y1_n |
Y2_n |
Y3_n |
Y4_n |
Y5_n |
Y6_n |
Y7_n |
|
x |
1 |
x |
x |
x |
x |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
x |
x |
1 |
x |
x |
x |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
0 |
x |
x |
x |
x |
x |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
|
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
|
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
0 |
输入描述
input E1_n ,输出描述
output wire Y0_n ,Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module decoder_38(
input E1_n ,
input E2_n ,
input E3 ,
input A0 ,
input A1 ,
input A2 ,
output wire Y0_n ,
output wire Y1_n ,
output wire Y2_n ,
output wire Y3_n ,
output wire Y4_n ,
output wire Y5_n ,
output wire Y6_n ,
output wire Y7_n
);
reg [7:0]Y_tmp;
always@(*)
case({A2,A1,A0})
3'd0:Y_tmp=8'b11111110;
3'd1:Y_tmp=8'b11111101;
3'd2:Y_tmp=8'b11111011;
3'd3:Y_tmp=8'b11110111;
3'd4:Y_tmp=8'b11101111;
3'd5:Y_tmp=8'b11011111;
3'd6:Y_tmp=8'b10111111;
3'd7:Y_tmp=8'b01111111;
default:Y_tmp=8'b11111111;
endcase
assign {Y7_n,Y6_n,Y5_n,Y4_n,Y3_n,Y2_n,Y1_n,Y0_n}=(E3&(!E2_n)&(!E1_n))?
Y_tmp:8'b11111111;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns module decoder_38( input E1_n , input E2_n , input E3 , input A0 , input A1 , input A2 , output wire Y0_n , output wire Y1_n , output wire Y2_n , output wire Y3_n , output wire Y4_n , output wire Y5_n , output wire Y6_n , output wire Y7_n ); assign Y0_n = (~E3 | E2_n | E1_n) | ~(~A0 & ~A1 & ~A2); assign Y1_n = (~E3 | E2_n | E1_n) | ~(A0 & ~A1 & ~A2); assign Y2_n = (~E3 | E2_n | E1_n) | ~(~A0 & A1 & ~A2); assign Y3_n = (~E3 | E2_n | E1_n) | ~(A0 & A1 & ~A2); assign Y4_n = (~E3 | E2_n | E1_n) | ~(~A0 & ~A1 & A2); assign Y5_n = (~E3 | E2_n | E1_n) | ~(A0 & ~A1 & A2); assign Y6_n = (~E3 | E2_n | E1_n) | ~(~A0 & A1 & A2); assign Y7_n = (~E3 | E2_n | E1_n) | ~(A0 & A1 & A2); endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module decoder_38(
input E1_n ,
input E2_n ,
input E3 ,
input A0 ,
input A1 ,
input A2 ,
output wire Y0_n ,
output wire Y1_n ,
output wire Y2_n ,
output wire Y3_n ,
output wire Y4_n ,
output wire Y5_n ,
output wire Y6_n ,
output wire Y7_n
);
reg y0_n;
reg y1_n;
reg y2_n;
reg y3_n;
reg y4_n;
reg y5_n;
reg y6_n;
reg y7_n;
always @ (*) begin
if ((E3 == 0) | (E2_n == 1) | (E1_n == 1)) begin
y0_n = 1; y1_n = 1; y2_n = 1; y3_n = 1; y4_n = 1; y5_n = 1; y6_n = 1; y7_n = 1;
end
else begin
case ({A2, A1, A0})
3'b000: begin y0_n = 0; y1_n = 1; y2_n = 1; y3_n = 1; y4_n = 1; y5_n = 1; y6_n = 1; y7_n = 1; end
3'b001: begin y0_n = 1; y1_n = 0; y2_n = 1; y3_n = 1; y4_n = 1; y5_n = 1; y6_n = 1; y7_n = 1; end
3'b010: begin y0_n = 1; y1_n = 1; y2_n = 0; y3_n = 1; y4_n = 1; y5_n = 1; y6_n = 1; y7_n = 1; end
3'b011: begin y0_n = 1; y1_n = 1; y2_n = 1; y3_n = 0; y4_n = 1; y5_n = 1; y6_n = 1; y7_n = 1; end
3'b100: begin y0_n = 1; y1_n = 1; y2_n = 1; y3_n = 1; y4_n = 0; y5_n = 1; y6_n = 1; y7_n = 1; end
3'b101: begin y0_n = 1; y1_n = 1; y2_n = 1; y3_n = 1; y4_n = 1; y5_n = 0; y6_n = 1; y7_n = 1; end
3'b110: begin y0_n = 1; y1_n = 1; y2_n = 1; y3_n = 1; y4_n = 1; y5_n = 1; y6_n = 0; y7_n = 1; end
3'b111: begin y0_n = 1; y1_n = 1; y2_n = 1; y3_n = 1; y4_n = 1; y5_n = 1; y6_n = 1; y7_n = 0; end
endcase
end
end
assign Y0_n = y0_n;
assign Y1_n = y1_n;
assign Y2_n = y2_n;
assign Y3_n = y3_n;
assign Y4_n = y4_n;
assign Y5_n = y5_n;
assign Y6_n = y6_n;
assign Y7_n = y7_n;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module decoder_38(
input E1_n ,
input E2_n ,
input E3 ,
input A0 ,
input A1 ,
input A2 ,
output wire Y0_n ,
output wire Y1_n ,
output wire Y2_n ,
output wire Y3_n ,
output wire Y4_n ,
output wire Y5_n ,
output wire Y6_n ,
output wire Y7_n
);
assign {Y7_n,Y6_n,Y5_n,Y4_n,Y3_n,Y2_n,Y1_n,Y0_n}=({E3,E2_n,E1_n}==3'b100)?~(1<<{A2,A1,A0}):8'hff;
endmodule
Verilog 解法, 执行用时: 0ms, 内存消耗: 0KB, 提交时间: 2022-08-06
`timescale 1ns/1ns
module decoder_38(
input E1_n ,
input E2_n ,
input E3 ,
input A0 ,
input A1 ,
input A2 ,
output wire Y0_n ,
output wire Y1_n ,
output wire Y2_n ,
output wire Y3_n ,
output wire Y4_n ,
output wire Y5_n ,
output wire Y6_n ,
output wire Y7_n
);
/* reg [7:0] Y;
wire flag;
assign flag=E2_n|E1_n|(!E3);
always@(*) begin
if(flag) begin
Y=8'b1111_1111;
end
else begin
case({A2,A1,A0})
3'b000:Y=8'b1111_1110;
3'b001:Y=8'b1111_1101;
3'b010:Y=8'b1111_1011;
3'b011:Y=8'b1111_0111;
3'b100:Y=8'b1110_1111;
3'b101:Y=8'b1101_1111;
3'b110:Y=8'b1011_1111;
3'b111:Y=8'b0111_1111;
default:Y=8'b1111_1111;
endcase
end
end
assign {Y7_n,Y6_n,Y5_n,Y4_n,Y3_n,Y2_n,Y1_n,Y0_n}=Y;*/
wire E;
assign E = E3 & (!E2_n) & (!E1_n);
assign Y0_n = !(E & (!A2) & (!A1) & (!A0));
assign Y1_n = !(E & (!A2) & (!A1) & A0);
assign Y2_n = !(E & (!A2) & (A1) & (!A0));
assign Y3_n = !(E & (!A2) & (A1) & A0);
assign Y4_n = !(E & (A2) & (!A1) & (!A0));
assign Y5_n = !(E & (A2) & (!A1) & A0);
assign Y6_n = !(E & (A2) & (A1) & (!A0));
assign Y7_n = !(E & (A2) & (A1) & (A0));
endmodule